Fabrication method for fused multi-layer amorphous selenium sensor

Patent metadata

Field	Value
Publication number	US-10547015-B2
Application number	US-201715761187-A
Country	US
Kind code	B2
Filing date	Nov 30, 2017
Priority date	Dec 2, 2016
Publication date	Jan 28, 2020
Grant date	Jan 28, 2020

Abstract

A sensor including a layer of amorphous selenium (a-Se) and at least one charge blocking layer is formed by depositing the charge blocking layer over a substrate prior to depositing the amorphous selenium, enabling the charge blocking layer to be formed at elevated temperatures. Such a process is not limited by the crystallization temperature of a-Se, resulting in the formation of an efficient charge blocking layer, which enables improved signal amplification of the resulting device. The sensor can be fabricated by forming first and second amorphous selenium layers over separate substrates, and then fusing the a-Se layers at a relatively low temperature.

First claim

What is claimed is:

1. A method of fabricating a sensor, comprising:
forming a first charge blocking layer over a first substrate;
forming a first layer of amorphous selenium over the first charge blocking layer;
forming a second charge blocking layer over a second substrate;
forming a second layer of amorphous selenium over the second charge blocking layer;
contacting the first layer of amorphous selenium with the second layer of amorphous selenium to form a multi-layer structure;
heating the multi-layer structure to fuse the first layer of amorphous selenium to the second layer of amorphous selenium.

2. The method of claim 1 , wherein the first charge blocking layer and the second charge blocking layer each comprise an organic polymer.

3. The method of claim 1 , wherein the first charge blocking layer and the second charge blocking layer are formed by physical vapor deposition, chemical vapor deposition or solution-based deposition.

4. The method of claim 1 , wherein the first substrate comprises an electronic readout.

5. The method of claim 1 , wherein the first charge blocking layer is formed over a pixel electrode.

6. The method of claim 1 , wherein a thickness of the first layer of amorphous selenium is less than a thickness of the second layer of amorphous selenium.

7. The method of claim 1 , wherein at least one of the first layer of amorphous selenium and the second layer of amorphous selenium comprises doped amorphous selenium.

8. The method of claim 1 , wherein the second substrate comprises electroded glass or a scintillator.

9. The method of claim 1 , wherein at least one of the first substrate and the second substrate is a flexible substrate.

10. The method of claim 1 , further comprising forming a high voltage electrode over the second substrate prior to forming the second charge blocking layer.

11. The method of claim 1 , wherein the multi-layer structure is heated to a temperature between 35° C. and 60° C. to fuse the amorphous selenium layers.

12. The method of claim 1 , further comprising applying a compressive force to the multi-layer structure during the heating.

13. The method of claim 1 , wherein heating the multi-layer structure to fuse the first and second layers of amorphous selenium is performed under vacuum.

14. The method of claim 1 , wherein the fused layers of amorphous selenium are free of pores.

Assignees

• Univ New York State Res Found

Inventors

• Scheuermann James
• Zhao Wei

Classifications

• G01T1/247

  Detector read-out circuitry (for processing gain or off-set correction H04N) · CPC title

• G01T1/241

  Electrode arrangements, e.g. continuous or parallel strips or the like · CPC title

• G01T1/24

  with semiconductor detectors · CPC title

• G01T1/20

  with scintillation detectors · CPC title

• G01T1/2018

  Scintillation-photodiode combinations · CPC title