Photodetector having a tunable junction region doping profile configured to improve contact resistance performance

Patent metadata

Field	Value
Publication number	US-10546971-B2
Application number	US-201815867121-A
Country	US
Kind code	B2
Filing date	Jan 10, 2018
Priority date	Jan 10, 2018
Publication date	Jan 28, 2020
Grant date	Jan 28, 2020

Abstract

Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a semiconductor material that includes a first type of majority carrier. A doping enhancement layer is formed over a region of the semiconductor material, wherein the doping enhancement layer includes a first type of material. A dopant is accelerated sufficiently to drive the dopant through the doping enhancement layer into the region of the semiconductor material. Accelerating the dopant through the doping enhancement layer also drives some of the first type of material from the doping enhancement layer into the region of the semiconductor material. The dopant within the region and the first type of material within the region contribute to the region having a second type of majority carrier.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming a semiconductor material comprising a first type of majority carrier;
forming a sacrificial layer over a covered region of the semiconductor material such that a first region of the semiconductor material is exposed;
wherein the sacrificial layer comprises a sacrificial metal layer and a passivation layer between the sacrificial metal layer and the semiconductor material;
wherein the passivation layer prevents electrical conduction between the semiconductor material and the sacrificial metal layer;
forming a doping enhancement layer over the covered region and the first region of the semiconductor material, wherein the sacrificial layer is between the doping enhancement layer and the semiconductor material, wherein the doping enhancement layer comprises a first type of material; and
accelerating a dopant sufficiently to drive the dopant through the doping enhancement layer and into:
the sacrificial layer; and
the first region to create a doped first region;

wherein accelerating the dopant through the doping enhancement layer drives the dopant into the sacrificial layer but does not drive the dopant through the sacrificial layer into the semiconductor material;
wherein accelerating the dopant through the doping enhancement layer also drives the first type of material from the doping enhancement layer into the doped first region of the semiconductor material;
wherein the dopant within the doped first region contributes to the doped first region comprising a second type of majority carrier; and
wherein the first type of material within the doped first region also contributes to the doped first region comprising the second type of majority carrier.

2. The method of claim 1 , wherein:
the semiconductor material comprises the doped first region and a second region; and
an interface between the doped first region and the second region comprises a p-n junction.

3. The method of claim 1 , wherein:
the doped first region comprises a doped first sub-region adjacent a first surface of the semiconductor material;
the doped first region further comprises a doped second sub-region positioned outside of the doped first sub-region; and
a concentration of the dopant and the first type of material within the doped first sub-region is greater than a concentration of the dopant and the first type of material in the doped second sub-region.

4. The method of claim 1 , wherein accelerating the dopant through the doping enhancement layer drives the dopant into the sacrificial metal layer of the sacrificial layer.

5. The method of claim 3 further comprising:
removing the doping enhancement layer from over the doped first region of the semiconductor material;
removing at least a portion of the sacrificial layer from over the covered region of the semiconductor material; and
communicatively coupling a first contact to the first surface of semiconductor material.

6. The method of claim 5 further comprising communicatively coupling a second contact to a second surface of the semiconductor material.

7. The method of claim 1 , wherein the semiconductor material comprises indium antimonide.

8. The method of claim 7 , wherein the first type of material comprises a first p-type dopant.

9. The method of claim 8 , wherein the dopant comprises a second p-type dopant.

10. A method of forming a semiconductor device, the method comprising:
forming a semiconductor material comprising a first type of majority carrier;
forming a sacrificial layer over a covered region of the semiconductor material such that a first region of the semiconductor material is exposed;
wherein the sacrificial layer comprises a sacrificial metal layer and a passivation layer between the sacrificial metal layer and the semiconductor material;
wherein the passivation layer prevents electrical conduction between the semiconductor material and the sacrificial metal layer;
forming a doping enhancement layer over the covered region and the first region of the semiconductor material, wherein the sacrificial layer is between the doping enhancement layer and the semiconductor material, wherein the doping enhancement layer comprises a first type of material; and
applying an ion implantation process to accelerate a dopant sufficiently to drive the dopant through the doping enhancement layer into:
the sacrificial layer; and
the first region to create a doped first region;

wherein accelerating the dopant through the doping enhancement layer drives the dopant into the sacrificial layer but does not drive the dopant through the sacrificial layer into the semiconductor material;
wherein applying the ion implantation process to accelerate the dopant through the doping enhancement layer also drives the first type of material from the doping enhancement layer into the doped first region of the semiconductor material;
wherein the dopant within the doped first region contributes to the doped first region comprising a second type of majority carrier; and
wherein the first type of material within the doped first region also contributes to the doped first region comprising the second type of majority carrier.

11. The method of claim 10 , wherein:
the semiconductor material comprises the doped first region and a second region; and
an interface between the doped first region and the second region comprises a p-n junction.

12. The method of claim 10 , wherein:
the doped first region comprises a doped first sub-region adjacent a first surface of the semiconductor material;
the doped first region further comprises a doped second sub-region positioned outside of the doped first sub-region; and
a concentration of the dopant and the first type of material within the doped first sub-region is greater than a concentration of the dopant and the first type of material in the doped second sub-region.

13. The method of claim 10 , wherein accelerating the dopant through the doping enhancement layer drives the dopant into the sacrificial metal layer of the sacrificial layer.

14. The method of claim 12 further comprising:
removing the doping enhancement layer from over the doped first region of the semiconductor material;
removing at least a portion of the sacrificial layer from over the covered region of the semiconductor material;
communicatively coupling a first contact to the first surface of the semiconductor material; and
communicatively coupling a second contact to a second surface of the semiconductor material.

15. The method of claim 10 , wherein the semiconductor material comprises indium antimonide.

16. The method of claim 15 , wherein the first type of material comprises a first p-type dopant.

17. The method of claim 16 , wherein the dopant comprises a second p-type dopant.

18. A method of forming a semiconductor device, the method comprising:
forming a semiconductor material comprising a first surface and a first type of majority carrier;
covering a portion of the first surface with a sacrificial layer such that a covered portion of the first surface is formed and such that a first portion of the first surface exposed;
wherein the sacrificial layer comprises a sacrificial metal layer and a passivation layer between the sacrificial metal layer and the semiconductor material;
wherein the passivation layer prevents electrical conduction between the semiconductor material and the sacrificial metal layer;
forming a doping enhancement layer over the covered portion and the first portion o

Assignees

• IBM

Inventors

• De Souza Joel P
• Li Ning
• Sadana Devendra
• Yao Yao

Classifications

• H10P30/212

  Through-implantation · CPC title

• H10P30/206

  into Group III-V semiconductors · CPC title

• H10P30/22

  using masks · CPC title

• H01L31/184 Primary

  Electricity · mapped topic

• H01L21/266

  Electricity · mapped topic