Transistor and display device having the same

Patent metadata

Field	Value
Publication number	US-10546959-B2
Application number	US-201715662502-A
Country	US
Kind code	B2
Filing date	Jul 28, 2017
Priority date	Aug 5, 2016
Publication date	Jan 28, 2020
Grant date	Jan 28, 2020

Abstract

A transistor includes a gate electrode, a semiconductor layer overlapping the gate electrode, the semiconductor layer including an oxide semiconductor, and a source electrode and a drain electrode spaced apart from the source electrode, wherein the source and drain electrodes are connected to the semiconductor layer. The semiconductor layer includes a plurality of layers, wherein a crystallinity of a layer of the plurality of layers of the semiconductor layer is a ratio of a crystalline oxide semiconductor, included in the layer of the plurality of layers of the semiconductor layer, to an amorphous oxide semiconductor, included in the layer of the plurality of layers of the semiconductor layer. A first layer of the plurality of layers of the semiconductor layer has a different crystallinity with respect to a second layer of the plurality of layers of the semiconductor layer.

First claim

What is claimed is:

1. A transistor, comprising:
a gate electrode;
a semiconductor layer overlapping the gate electrode, the semiconductor layer including an oxide semiconductor; and
a source electrode and a drain electrode spaced apart from the source electrode, wherein the source and drain electrodes are connected to the semiconductor layer,
wherein the semiconductor layer includes a plurality of layers,
wherein a crystallinity of a layer of the plurality of layers of the semiconductor layer is a ratio of a crystalline oxide semiconductor, included in the layer of the plurality of layers of the semiconductor layer, to an amorphous oxide semiconductor, included in the layer of the plurality of layers of the semiconductor layer, and
wherein the semiconductor layer includes:
a first layer, wherein the first layer has a first crystallinity;
a second layer disposed on the first layer, wherein the second layer has a second crystallinity, wherein the second crystallinity is greater than the first crystallinity; and
a third layer disposed on the second layer, wherein the third layer has a third crystallinity, wherein the third crystallinity is greater than the second crystallinity,
wherein the first layer, the second layer, and the third layer are sequentially stacked.

2. The transistor of claim 1 , wherein a thickness of the third layer is about 20% to about 30% of an entire thickness of the semiconductor layer.

3. The transistor of claim 2 , wherein the third crystallinity is about 100%.

4. The transistor of claim 2 , wherein the third layer includes a first region that overlaps the gate electrode and a second region that does not overlap the gate electrode, wherein a thickness of the first region is smaller than a thickness of the second region.

5. The transistor of claim 4 , wherein the thickness of the first region is 0% to about 10% of the thickness of the second region.

6. The transistor of claim 2 , wherein the crystalline oxide semiconductor included in the third layer includes crystals, and the crystals have a c-axis.

7. The transistor of claim 6 , wherein, in the second layer,
a crystallinity of a region adjacent to the third layer is higher than a crystallinity of a region adjacent to the first layer.

8. The transistor of claim 7 , wherein the first crystallinity is 0%.

9. The transistor of claim 8 , wherein a thickness of the first layer is about 10% to about 20% of the entire thickness of the semiconductor layer.

10. A display device, comprising:
a substrate;
a first transistor disposed on the substrate; and
a light emitting device connected to the first transistor,
wherein the first transistor includes:
a gate electrode;
a semiconductor layer overlapping the gate electrode, wherein the semiconductor layer includes an oxide semiconductor; and
a source electrode and a drain electrode spaced apart from the source electrode, wherein the source and drain electrodes are connected to the semiconductor layer,

wherein the semiconductor layer includes a plurality of layers,
wherein a crystallinity of a given layer of the plurality of layers of the semiconductor layer is a ratio of a crystalline oxide semiconductor, included in the given layer of the plurality of layers of the semiconductor layer, to an amorphous oxide semiconductor, included in the given layer of the plurality of layers of the semiconductor layer, and
wherein a first layer of the plurality of layers of the semiconductor layer has a different crystallinity with respect to a second layer of the plurality of layers of the semiconductor layer,
wherein the semiconductor layer includes:
the first layer, wherein the first layer has a first crystallinity;
the second layer disposed on the first layer, wherein the second layer has a second crystallinity, wherein the second crystallinity is greater than the first crystallinity;
and a third layer disposed on the second layer, wherein the third layer has a third crystallinity, wherein the third crystallinity is greater than the second crystallinity,
wherein the first layer, the second layer, and the third layer are sequentially stacked.

11. The display device of claim 10 , wherein the third crystallinity is 100%.

12. The display device of claim 11 , wherein a thickness of the third layer is about 20% to about 30% of an entire thickness of the semiconductor layer.

13. The display device of claim 12 , wherein the third layer includes a first region that overlaps the gate electrode and a second region that does not overlap the gate electrode, wherein a thickness of the first region is smaller than a thickness of the second region.

14. The display device of claim 12 , wherein the crystalline oxide semiconductor included in the third layer includes crystals, and the crystals have a c-axis.

15. The display device of claim 13 , wherein, in the second layer,
a crystallinity of a region adjacent to the third layer is higher than a crystallinity of a region adjacent to the first layer.

16. The display device of claim 15 , wherein the first crystallinity is 0%, and wherein a thickness of the first layer is about 10% to about 20% of the entire thickness of the semiconductor layer.

17. The display device of claim 16 , wherein the light emitting device includes:
a first electrode connected to the transistor;
an emitting layer disposed on the first electrode; and
a second electrode disposed on the emitting layer.

18. A transistor, comprising:
a gate electrode;
a first semiconductor layer, a second semiconductor layer and a third semiconductor layer stacked on each other such that the second semiconductor layer is disposed between the first and third semiconductor layers, wherein at least the second and third semiconductor layers, from among a group of the first, second and third semiconductor layers, overlap the gate electrode, and wherein each of the first, second and third semiconductor layers includes an oxide semiconductor; and
a source electrode and a drain electrode spaced apart from each other, wherein the source and drain electrodes are connected to the third semiconductor layer,
wherein a ratio of a crystalline oxide semiconductor to an amorphous oxide semiconductor included in the third semiconductor layer is higher than a ratio of a crystalline oxide semiconductor to an amorphous oxide semiconductor included in the second semiconductor layer, and
wherein the ratio of the crystalline oxide semiconductor to the amorphous oxide semiconductor included in the third semiconductor layer is higher than a ratio of a crystalline oxide semiconductor to an amorphous oxide semiconductor included in the first semiconductor layer.

19. The transistor of claim 18 , wherein the ratio of the crystalline oxide semiconductor to the amorphous oxide semiconductor included in the second semiconductor layer is higher than the ratio of the crystalline oxide semiconductor to the amorphous oxide semiconductor included in the first semiconductor layer.

Assignees

• Samsung Display Co Ltd

Inventors

• Woo Sung Wook
• Lee Chang Ho
• Rho Kyung Lae
• Lee Doo Hyoung
• Jo Sung Chan
• Sohn Sang Woo
• Shin Sang Won
• Jeong Soo Im
• Jeong Chang Yong

Classifications

• H01L29/045

  Electricity · mapped topic

• H01L29/78693 Primary

  Electricity · mapped topic

• H01L29/247

  Electricity · mapped topic

• H01L29/1033

  Electricity · mapped topic

• H01L29/78696

  Electricity · mapped topic