High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency

Patent metadata

Field	Value
Publication number	US-10546771-B2
Application number	US-201715727723-A
Country	US
Kind code	B2
Filing date	Oct 9, 2017
Priority date	Oct 26, 2016
Publication date	Jan 28, 2020
Grant date	Jan 28, 2020

Abstract

A multilayer semiconductor on insulator structure is provided in which the handle substrate and an epitaxial layer in interfacial contact with the handle substrate comprise electrically active dopants of opposite type. The epitaxial layer is depleted by the handle substrate free carriers, thereby resulting in a high apparent resistivity, which improves the function of the structure in RF devices.

First claim

What is claimed is:

1. A method of preparing a multilayer substrate, the method comprising:
epitaxially depositing an epitaxial layer directly on the front surface of a single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate comprises two major, generally parallel surfaces, one of which is the front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, a circumferential edge joining the front surface and the back surface of the single crystal semiconductor handle substrate, a central plane between the front surface and the back surface of the single crystal semiconductor handle substrate, and a bulk region between the front and back surfaces of the single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate has a minimum bulk region resistivity of at least about 500 ohm-cm and further wherein the single crystal semiconductor handle substrate has a handle crystal orientation and wherein the epitaxial layer has a resistivity between about 100 ohm-cm and about 5000 ohm-cm and further wherein the epitaxial layer has a crystal orientation that is the same as the handle crystal orientation:
depositing a charge trapping layer directly on the epitaxial layer, the charge trapping layer comprising polycrystalline silicon having a resistivity of at least about 3000 ohm-cm; and
bonding a dielectric layer directly on a front surface of a single crystal semiconductor donor substrate to the charge trapping layer to thereby form a bonded structure, wherein the single crystal semiconductor donor substrate comprises two major, generally parallel surfaces, one of which is the front surface of the semiconductor donor substrate and the other of which is a back surface of the semiconductor donor substrate, a circumferential edge joining the front and back surfaces of the semiconductor donor substrate, and a central plane between the front and back surfaces of the semiconductor donor substrate, wherein the single crystal semiconductor donor substrate comprises a cleave plane.

2. The method of claim 1 wherein the single crystal semiconductor handle substrate comprises single crystal silicon.

3. The method of claim 1 wherein the single crystal semiconductor donor substrate comprises single crystal silicon.

4. The method of claim 1 wherein the single crystal semiconductor handle substrate has a bulk resistivity between about 1000 Ohm-cm and about 100,000 Ohm-cm.

5. The method of claim 1 wherein the single crystal semiconductor handle substrate has a bulk resistivity between about 1000 Ohm-cm and about 6,000 Ohm-cm.

6. The method of claim 1 wherein the single crystal semiconductor handle substrate comprises an electrically active dopant selected from the group consisting of boron, aluminum, gallium, indium, and any combination thereof.

7. The method of claim 1 wherein the epitaxial layer has a resistivity between about 200 ohm-cm and about 2000 ohm-cm.

8. The method of claim 1 wherein the epitaxial layer has a resistivity between about 400 ohm-cm and about 1000 ohm-cm.

9. The method of claim 1 wherein the epitaxial layer comprises silicon and an electrically active dopant selected from the group consisting of arsenic, phosphorus, antimony, and any combination thereof.

10. The method of claim 9 wherein the epitaxial layer comprising silicon is between about 0.2 micrometers and about 20 micrometers thick.

11. The method of claim 9 wherein the epitaxial layer comprising silicon is between about 0.5 micrometers and about 10 micrometers thick.

12. The method of claim 1 wherein the epitaxial layer comprises silicon doped with carbon at a carbon concentration between about 0.1 mole % and about 5 mole %.

13. The method of claim 12 wherein the epitaxial layer comprises silicon doped with carbon at a carbon concentration between about 0.5 mole % and about 2 mole %.

14. The method of claim 12 wherein the epitaxial layer comprising silicon doped with carbon is between about 0.1 micrometers and about 10 micrometers thick.

15. The method of claim 1 wherein the charge trapping layer has a resistivity of at least about 7000 ohm-cm.

16. The method of claim 1 further comprising forming an insulating layer on the charge trapping layer prior to bonding with the dielectric layer on the front surface of the single crystal semiconductor donor substrate, wherein the insulating layer comprises semiconductor oxide or semiconductor oxynitride.

17. The method of claim 1 wherein the dielectric layer comprises a material selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide, and a combination thereof.

18. The method of claim 1 further comprising heating the bonded structure at a temperature and for a duration sufficient to strengthen the bond between the dielectric layer of the single crystal semiconductor donor substrate and the charge trapping layer on the front surface of the single crystal semiconductor handle substrate.

19. The method of claim 1 further comprising mechanically cleaving the bonded structure at the cleave plane of the single crystal semiconductor donor substrate to thereby prepare a cleaved structure comprising the single crystal semiconductor handle substrate, the epitaxial layer, the charge trapping layer, the dielectric layer, and a single crystal semiconductor device layer.

20. A method of preparing a multilayer substrate, the method comprising:
epitaxially depositing an epitaxial layer directly on the front surface of a single crystal semiconductor handle substrate, wherein the comprises single crystal semiconductor handle substrate two major, generally parallel surfaces, one of which is the front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, a circumferential edge joining the front surface and the back surface of the single crystal semiconductor handle substrate, a central plane between the front surface and the back surface of the single crystal semiconductor handle substrate, and a bulk region between the front and back surfaces of the single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate comprises an electrically active p-type dopant selected from the group consisting of boron, aluminum, gallium, indium, and any combination thereof and further wherein the single crystal semiconductor handle substrate has a handle crystal orientation and wherein the epitaxial layer comprises an electrically active n-type dopant selected from the group consisting of arsenic, phosphorus, antimony, and any combination thereof, wherein the concentration of the electrically active n-type dopant is less than about 1×10 14 atoms/cm 3 and further wherein the epitaxial layer has a crystal orientation that is the same as the handle crystal orientation:
depositing a charge trapping layer directly on the epitaxial layer, the charge trapping layer comprising polycrystalline silicon; and
bonding a dielectric layer directly on a front surface of a single crystal semiconductor donor substrate to the charge trapping layer to thereby form a bonded structure, wherein the single crystal semiconductor donor substrate comprises two major, generally parallel surfaces, one of which is the front surface of the semicond

Assignees

• Sunedison Semiconductor Ltd Uen201334164H
• Globalwafers Co Ltd

Inventors

• Wang Gang
• Libbert Jeffrey L
• Thomas Shawn George
• Liu Qingmin

Classifications

• H10P14/3444

  P-type · CPC title

• H10P14/3442

  N-type · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3258

  Crystal orientation · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title