Source and drain formation using self-aligned processes

Patent metadata

Field	Value
Publication number	US-10541135-B2
Application number	US-201816162535-A
Country	US
Kind code	B2
Filing date	Oct 17, 2018
Priority date	Nov 30, 2017
Publication date	Jan 21, 2020
Grant date	Jan 21, 2020

Abstract

An approach to deposit, by a self-aligning process, a layer of graphene on a gate formed on a dielectric layer on a semiconductor substrate where the gate includes a metal catalyst material. The approach includes removing a portion of the dielectric layer and a portion of the semiconductor substrate not under the gate and depositing, by a self-aligning atomic layer deposition process, a layer of a material capable of creating a source and a drain in a semiconductor device on exposed surfaces of the semiconductor substrate and the dielectric layer. The approach includes removing the layer of graphene from the gate, and, then removing a portion of the layer of the material capable of creating the source and the drain in the semiconductor device.

First claim

The invention claimed is:

1. A method of fabricating a semiconductor device, comprising:
depositing a layer of graphene on a gate formed on a dielectric layer on a semiconductor substrate, wherein the gate includes a metal catalyst material for graphene deposition;
removing an exposed portion of the dielectric layer and removing a first portion of the semiconductor substrate not under the gate, wherein a second portion of the semiconductor substrate remains under the portion of the semiconductor substrate removed;
depositing a layer of a material on exposed surfaces of the dielectric layer and the semiconductor substrate, wherein the layer of the material creates a source and a drain in a semiconductor device;
removing the layer of graphene from the gate; and
removing a portion of the layer of the material creating the source and the drain, wherein the portion of the layer of the material creating the source and the drain is removed adjacent to a vertical edge of the portion of the dielectric layer remaining under the gate.

2. The method of claim 1 , wherein the layer of graphene is deposited by a self-aligning deposition process on the gate using a chemical vapor deposition process.

3. The method of claim 1 , wherein the layer of graphene provides a mask for selectively depositing, by an atomic layer deposition process, the layer of the material creating the source and the drain in the semiconductor device.

4. The method of claim 1 , wherein the layer of graphene is a single molecular layer of carbon atoms.

5. The method of claim 1 , wherein the layer of graphene is composed of multiple molecular layers of carbon atoms.

6. The method of claim 1 , wherein the dielectric layer is composed of a high dielectric constant material.

7. The method of claim 1 , wherein the semiconductor substrate is composed of at least one of: a group IV semiconductor material, a group III-V semiconductor material, or a group II-VI semiconductor material.

8. The method of claim 1 , wherein the semiconductor substrate is composed of a group III-V semiconductor material.

9. The method of claim 1 , wherein the semiconductor substrate is composed of InGaAs.

10. The method of claim 1 , wherein the layer of the material creating the source and the drain, deposited by a self-aligning deposition process, is a zinc oxide material doped with aluminum.

11. The method of claim 1 , wherein the layer of the material creating the source and the drain does not deposit on the layer of graphene.

12. The method of claim 1 , wherein removing the portion of the layer of the material creating the source and the drain includes using a reactive ion etch for removal of the portion of the layer of the material creating the source and the drain.

13. The method of claim 1 , wherein providing a portion of the layer of the material creating the source and the drain remaining on each vertical edge of the semiconductor substrate, and providing the layer of the material creating the source and the drain remaining on surface of the second portion of the semiconductor substrate.

14. The method of claim 1 , further comprising forming metal contacts and completing semiconductor device processing for back-end-of-line processing for semiconductor device formation.

15. The method of claim 1 , wherein the semiconductor device is a metal-oxide semiconductor field-effect transistor.

Assignees

• IBM

Inventors

• Kim Seyoung
• Lee Yun Seog
• Sadana Devendra
• De Souza Joel

Classifications

• H10P50/246

  of Group III-V materials · CPC title

• H10P14/3438

  Doping during depositing · CPC title

• H10P14/3426

  Oxides · CPC title

• H10P14/3406

  Carbon, e.g. diamond-like carbon · CPC title

• H10P14/3241

  being conductive materials · CPC title