Dual mode memory array security apparatus, systems and methods

Patent metadata

Field	Value
Publication number	US-10541016-B2
Application number	US-201816120107-A
Country	US
Kind code	B2
Filing date	Aug 31, 2018
Priority date	Jul 8, 2015
Publication date	Jan 21, 2020
Grant date	Jan 21, 2020

Abstract

Read-only (“RO”) data consisting of a physically unclonable function (“PUF”) pattern is written to a ferroelectric random-access memory (“FRAM”) memory array. The FRAM array is baked to imprint the PUF pattern with a selected average depth of imprint and a corresponding average read reliability. The average depth of imprint and corresponding average read reliability are determined during testing after baking. The PUF pattern as read after baking is compared to the PUF pattern as written prior to baking. Additional PUF pattern writing and baking cycles may be performed until the average depth of imprint and associated read reliability reach a first selected level. Integrated circuits determined to be over-imprinted by exceeding a second selected level may be rejected. The first and second levels of PUF pattern imprint are selected such as to produce FRAM arrays with a unique fingerprint for each individual FRAM array-containing integrated circuit.

First claim

What is claimed is:

1. A system state verification apparatus, comprising:
a dual-mode ferroelectric random access memory (“FRAM”) array capable of storing an imprinted read-only (“RO”) data bit and a non-imprinted read/write (“R/W”) data bit per array storage cell, the FRAM array imprinted with RO data representing a predetermined state of a system to be verified;
integrity verification logic communicatively coupled to the FRAM array to receive a system state verification request and to sequence RO mode access commands to the FRAM array in order to read the RO data representing the predetermined state; and
system state compare logic coupled to the integrity verification logic to receive the RO data representing the predetermined state, to receive data representing a detected system state, and to compare the RO data representing the predetermined state to the data representing the detected system state.

2. The system state verification apparatus of claim 1 , further comprising:
an output of the integrity verification logic to send at least one of a signal or at least one data bit back to the system to be verified to indicate whether the data representing the detected system state matches the RO data representing the predetermined state.

3. The system state verification apparatus of claim 1 , further comprising:
a stored system state buffer coupled to the system state compare logic to store the RO data representing the predetermined state and to send the RO data to the system state compare logic.

4. The system state verification apparatus of claim 1 , further comprising:
authentication logic coupled to the integrity verification logic to receive an authentication request for RO mode access, to authenticate the RO mode access request, and to pass the system state verification request to the integrity verification logic following authentication.

5. The system state verification apparatus of claim 1 , the FRAM array further comprising:
a plurality of 2T/2C FRAM storage cells, each FRAM cell consisting of two half-cells; and
a switching matrix coupled to each FRAM storage cell to switch a bit line associated with each half-cell for write access to the FRAM cell and read access from the FRAM cell.

6. The system state verification apparatus of claim 5 , the FRAM array further comprising:
dual mode state control logic coupled to the switching matrix and to the integrity verification logic to control switches associated with the switching matrix to enable full-cell read access and both full-cell and half-cell write access and to sequence the switches according to a first sequence to perform read operations of read/write (“R/W”) data and to sequence the switches according to a second sequence to perform read operations of the imprinted RO data.

7. A method of manufacturing a dual mode double cell (2T/2C) ferroelectric random access memory (FRAM) array capable of storing an imprinted read-only (“RO”) data bit and a non-imprinted read/write (“R/W”) data bit per array storage cell, the FRAM array imprinted with a physically unclonable function (“PUF”) pattern, comprising:
performing full-cell writes of the PUF pattern to storage cells of the FRAM array; and
baking the FRAM array at a selected temperature for a selected period of time to imprint the RO data to the storage cells with a selected average depth of imprint and a corresponding average read reliability.

8. The method of manufacturing a dual mode double cell FRAM array of claim 7 , further comprising:
selecting a biasing data set to write as the PUF pattern.

9. The method of manufacturing a dual mode double cell FRAM array of claim 7 , further comprising:
performing testing operations on cells of the FRAM array to determine the average read reliability.

10. The method of manufacturing a dual mode double cell FRAM array of claim 9 , the testing operations further comprising:
performing a plurality of RO mode read operations on the imprinted cells to determine an apparent imprinted state of each cell at each read operation.

11. The method of manufacturing a dual mode double cell FRAM array of claim 10 , each of the plurality of RO mode read operations further comprising:
writing each of two half-cells of a FRAM cell from which imprinted data is to be read with a predetermined bit state;
sensing a polarity of a voltage difference between bit lines of the two half-cells during a full-cell read operation; and
interpreting an apparent state of the imprinted data bit according to the voltage difference.

12. The method of manufacturing a dual mode double cell FRAM array of claim 10 , the testing operations further comprising:
For each read operation, comparing the RO data to the apparent imprinted state.

13. The method of manufacturing a dual mode double cell FRAM array of claim 12 , the testing operations further comprising:
calculating the average RO data read reliability by performing averaging operations on results of the compare operations.

14. The method of manufacturing a dual mode double cell FRAM array of claim 13 , further comprising:
determining whether the average read reliability is greater than or equal to a first selected level; and
re-writing the RO data to be imprinted and performing at least one additional baking cycle if the average read reliability is less than the first selected level.

15. The method of manufacturing a dual mode double cell FRAM array of claim 14 , further comprising:
determining whether the average read reliability is greater than or equal to a second selected level if the average read reliability is greater than or equal to the first selected level; and
rejecting an integrated circuit containing the FRAM array if the average read reliability is greater than or equal to the second selected level.

Assignees

• Texas Instruments Inc

Inventors

• Juvekar Chiraag
• Kwong Joyce
• Bittlestone Clive
• Ramaswamy Srinath

Classifications

• G09C1/00

  Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) · CPC title

• G11C11/221

  using ferroelectric capacitors · CPC title

• H04L9/3278

  using physically unclonable functions [PUF] · CPC title

• G11C11/2277

  Verifying circuits or methods · CPC title

• G11C11/2273

  Reading or sensing circuits or methods · CPC title