Coordination of cache and memory reservation

Patent metadata

Field	Value
Publication number	US-10540285-B2
Application number	US-201916390307-A
Country	US
Kind code	B2
Filing date	Apr 22, 2019
Priority date	Jul 12, 2017
Publication date	Jan 21, 2020
Grant date	Jan 21, 2020

Abstract

A method for coordinating cache and memory reservation in a computerized system includes identifying at least one running application, recognizing the at least one application as a latency-critical application, monitoring information associated with a current cache access rate and a required memory bandwidth of the at least one application, allocating a cache partition, a size of the cache partition corresponds to the cache access rate and the required memory bandwidth of the at least one application, defining a threshold value including a number of cache misses per time unit, determining a reduction of cache misses per time unit, in response to the reduction of cache misses per time unit being above the threshold value, retaining the cache partition, assigning a priority of scheduling memory request including a medium priority level, and assigning a memory channel to the at least one application to avoid memory channel contention.

First claim

What is claimed is:

1. A computer system for coordinating cache and memory reservation in a computerized system comprising a cache memory, a memory and a memory controller, the computer system comprising:
one or more processors, one or more computer-readable memories, one or more computer-readable tangible storage devices, and program instructions stored on at least one of the one or more storage devices for execution by at least one of the one or more processors via at least one of the one or more memories, wherein the computer system is capable of performing a method comprising:
detecting a first plurality of virtual machines and a second plurality of virtual machines in the computerized system, wherein the first plurality of virtual machines and the second plurality of virtual machines communicate with the memory through the cache memory and a plurality of memory channels, wherein the first plurality of virtual machines runs latency-critical services, and the second plurality of virtual machines runs non-critical services;
based on the second plurality of virtual machines running the non-critical services, assigning a low memory request priority;
based on the first plurality of virtual machines running the latency-critical services, determining a current cache access rate and a required memory bandwidth of the first plurality of virtual machines;
based on the determined current cache access rate and the required memory bandwidth, proportionally allocating a cache partition to the first plurality of virtual machines, wherein a size of the cache partition corresponds to the determined cache access rate and the required memory bandwidth;
defining a threshold value comprising a number of cache misses per time unit, wherein the threshold value helps determining whether an improvement caused by the cache partitioning is significant;
based on the number of cache misses per time unit being above the threshold value, identifying one or more virtual machines in the first plurality of virtual machines as cache-bound and retaining the cache partition;
receiving a memory request;
based on the one or more virtual machines in the first plurality of virtual machines being identified as cache-bound, assigning a medium priority for scheduling the memory request;
based on the number of cache misses per time unit being below the threshold value, identifying one or more virtual machines in the first plurality of virtual machines as bandwidth-bound and removing the cache partition;
based on the one or more virtual machines in the first plurality of virtual machines being identified as bandwidth-bound, assigning a high priority for scheduling the memory request, wherein a bandwidth-bound virtual machine comprises a higher memory bandwidth demand than a cache-bound virtual machine;
determining whether free memory channels are available;
based on determining that a number of free memory channels is less than the first plurality of virtual machines, assigning at least one cache-bound virtual machine and at least one bandwidth bound virtual machine to the same memory channel; and
based on determining that the number of free memory channels exceeds the first plurality of virtual machines, preventing two or more bandwidth-bound virtual machines from being assigned to the same memory channel, and assigning a mixed grouping of bandwidth-bound virtual machines and cache-bound virtual machines to the same memory channel such that an aggregate bandwidth usage of the mixed grouping is the lowest.

Assignees

• IBM

Inventors

• Birke Robert
• Chen Yiyu
• Rameshan Navaneeth
• Schmatz Martin

Classifications

• G06F2009/45583

  Memory management, e.g. access or allocation · CPC title

• G06F12/0831 Primary

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title

• G06F12/0804

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F12/084

  with a shared cache · CPC title

• G06F12/0877

  Cache access modes · CPC title