Method and apparatus for improving computer cache performance and for protecting memory systems against some side channel attacks

Patent metadata

Field	Value
Publication number	US-9396135-B2
Application number	US-201213458145-A
Country	US
Kind code	B2
Filing date	Apr 27, 2012
Priority date	May 18, 2011
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

A physical cache memory that is divided into one or more virtual segments using multiple circuits to decode addresses is provided. An address mapping and an address decoder is selected for each virtual segment. The address mapping comprises two or more address bits as set indexes for the virtual segment and the selected address bits are different for each virtual segment. A cache address decoder is provided for each virtual segment to enhance execution performance of programs or to protect against the side channel attack. Each physical cache address decoder comprises an address mask register to extract the selected address bits to locate objects in the virtual segment. The foregoing can be implemented as a method or apparatus for protecting against a side channel attack.

First claim

What is claimed is:

1. An apparatus comprising:
one or more processors or cores;
a physical memory communicably coupled to the processor(s) or core(s), wherein each location within the physical memory has a physical memory address;
one or more physical cache memories communicably coupled to the processor(s) and the physical memory;
two or more address mappings associated with each physical cache memory, wherein each of the two or more address mappings divide the physical memory address into at least a first set of address bits and a second set of address bits, the first set of address bits comprising a combination of two or more address bits from the physical memory address that are used as a set index to locate a program object in the physical cache memory, the second set of address bits are used as a tag to correctly identify a data in the physical cache memory with the physical memory address, a total number of bits used as the set index is less than a total number of bits in the physical memory address and the set index for the two or more address mappings are different;
an address decoder associated with each address mapping; and
a programmable address mask register with each address decoder that extracts (a) the set index from the physical memory address of the program object using changeable mask values which identify the address bits of the set index, and (b) the tag from the physical memory address of the program object using a complement of the changeable mask values which identify the address bits of the tag.

2. The apparatus as recited in claim 1 , wherein the changeable mask values are chosen and/or changed by a control software.

3. The apparatus as recited in claim 1 , wherein the changeable mask values are preset, selected at random, dynamically selected or selected based on one or more criteria.

4. The apparatus as recited in claim 1 , wherein the changeable mask values are chosen to minimize conflicts in the placement of data in cache memories.

5. The apparatus as recited in claim 1 , wherein the changeable mask values are chosen to create a plurality of cache partitions, each partition dedicated to a specific object, function, task or processor (core).

6. The apparatus as recited in claim 5 , wherein each address mapping created by the changeable mask values is restricted to a portion of the physical cache memory, thus creating multiple partitions within a cache and each partition may be dedicated for a specific object, function, program segment, task or processor.

7. The apparatus as recited in claim 1 , wherein the address mappings associated with the address decoders are used to collectively create a set associative cache memory.

8. The apparatus as recited in claim 7 , wherein the set associative cache includes any number of elements using as many address decoders as needed.

9. An apparatus comprising:
one or more processors or cores;
a physical memory communicably coupled to the processor(s) or core(s), wherein each location within the physical memory has a physical memory address;
a physical cache memory (Level 1 cache) communicably coupled to each of the processors;
two or more address mappings associated with each physical cache memory, wherein each of the two or more address mappings divide the physical memory address into at least a first set of address bits and a second set of address bits, the first set of address bits comprising a combination of two or more address bits from the physical memory address that are used as a set index to locate a program object in the physical cache memory, the second set of address bits are used as a tag to correctly identify a data in the physical cache memory with the physical memory address, a total number of bits used as the set index is less than a total number of bits in the physical memory address bits and the set index bits for the two or more address mappings are not identical;
an address decoder associated with each address mapping; and
a programmable address mask register with each address decoder that extracts (a) the set index from the physical memory address of the program object using changeable mask values which identify the address bits of the set index, and (b) the tag from the physical memory address of the program object using a complement of the changeable mask values which identify the address bits of the tag.

10. The apparatus as recited in claim 9 , wherein one of the cache address decoders of each Level-1 cache is dedicated to one or more encryption algorithms to prevent one or more side channel attacks.

11. The apparatus as recited in claim 10 , wherein the changeable mask values for the programmable address mask register associated with the address decoder dedicated for the encryption algorithm(s) is hidden.

12. The apparatus as recited in claim 10 , wherein the changeable mask values for the programmable address mask register of the dedicated address decoder is modified periodically or on program context switches.

13. The apparatus as recited in claim 9 , wherein each of the plurality of decoders associated with each Level-1 cache is dedicated to a specific program object or data structure.

14. The apparatus as recited in claim 13 , wherein the changeable mask values for the programmable address mask registers associated with the address decoders are chosen to optimize the placement of corresponding program object in Level-1 cache and minimize cache misses.

15. The apparatus as recited in claim 13 , wherein the changeable mask values for the programmable address mask registers of the plurality of decoders are collectively chosen to minimize Level-1 cache conflicts among the program objects.

16. The apparatus as recited in claim 9 , wherein each of the plurality of decoders associated with Level-1 cache is dedicated to a function or program segment.

17. The apparatus as recited in claim 16 , wherein the changeable mask values for the programmable address mask registers associated with the address decoders are chosen to optimize the Level-1 cache memory accesses and minimize cache misses caused by the corresponding function or program segment.

18. The apparatus as recited in claim 16 , wherein the changeable mask values for the programmable address mask registers of the plurality of decoders are collectively chosen to minimize the Level-1 cache memory conflicts among all program functions or segments.

19. The apparatus as recited in claim 9 , wherein each of the decoders associated with the Level-1 cache is dedicated to a task whenever multiple programs or tasks are executed on a single processor.

20. The apparatus as recited in claim 19 , wherein the changeable mask values for the programmable address mask registers associated with the address decoders are chosen to optimize the Level-1 cache memory accesses and minimize cache misses caused by the corresponding task or program.

21. The apparatus as recited in claim 19 , wherein the changeable mask values for the programmable address mask registers of the decoders are collectively chosen to minimize the Level-1 cache memory conflicts among all program functions or segments.

22. An apparatus comprising:
two or more processors or cores;
a physical memory communicably coupled to the processor(s) or cores, wherein each location within the physical memory has a physical memory address;
one or more physical cache memories (Level 2 cache or Last Level Cache) communicably coupled to the processor(s) or core(s);
two or more address mappings ass

Assignees

• Kavi Krishna M
• Univ North Texas

Inventors

• Kavi Krishna M

Classifications

• G06F12/1408 Primary

  by using cryptography (for digital transmission H04L9/00) · CPC title

• G06F12/0864

  using pseudo-associative means, e.g. set-associative or hashing · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F12/0897

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title

• G06F2212/1052

  Security improvement · CPC title