Dynamic instruction latency management in SIMD machines

Patent metadata

Field	Value
Publication number	US-10540260-B2
Application number	US-201815903393-A
Country	US
Kind code	B2
Filing date	Feb 23, 2018
Priority date	Feb 23, 2018
Publication date	Jan 21, 2020
Grant date	Jan 21, 2020

Abstract

In one example, an apparatus comprises processing circuitry to analyze a program at compile time to determine a set of latency parameters associated with instruction sets implemented to execute the program and select a latency management technique based at least in part on the set of latency parameters associated with instruction sets implemented to execute the program. Other examples may be described and claimed.

First claim

What is claimed is:

1. An apparatus comprising: a general purpose graphic processor, comprising:
an instruction cache to receive a stream of instructions generated by a graphics program;
an instruction unit to execute the stream of instructions;
a general-purpose graphics processing compute block comprising a plurality of graphics compute units;
a plurality of registers coupled to the plurality of graphics processing compute units;
a hardware unit to selectively enable the instruction unit to execute the stream of instructions out of order; and
a processor communicatively coupled to the general purpose graphics processor to:
select a first hardware thread count to be applied to the plurality of graphics compute units to execute the stream of instructions;
analyze the graphics program to be executed on the general purpose graphics processor at compile time to determine a set of latency parameters associated with the execution of the stream of instructions at the first hardware thread count;

select a latency management technique to be implemented by the general purpose graphics processor based at least in part on the set of latency parameters associated with instruction sets implemented to execute the program;
determine the set of latency parameters associated with instruction sets implemented to execute the program at a current hardware thread count;
determine a composite latency score for the program from the set of latency parameters at the current thread count; and
compare the composite latency score at the current hardware thread count to a threshold.

2. The apparatus of claim 1 , the processor to:
generate an instruction for the general purpose graphics processor to select a second hardware thread count, greater than the first hardware thread count.

3. The apparatus of claim 1 , the processor to:
set the hardware thread count for execution of the program to the current hardware thread when the composite latency score falls beneath the threshold.

4. The apparatus of claim 1 , the processor to:
generate an instruction for the general purpose graphics processor to enable out-of-order instruction scheduling for hardware executing the program.

5. An electronic device, comprising: a computer readable memory:
a graphics processor comprising;
an instruction cache to receive a stream of instructions generated by a graphics program;
an instruction unit to execute the stream of instructions;

a general-purpose graphics processing compute block comprising a plurality of graphics compute units;
a plurality of registers coupled to the plurality of graphics processing compute units;
a hardware unit to selectively enable the instruction unit to execute the stream of instructions out of order; and
a processor communicatively coupled to the general purpose graphics processor to:
select a first hardware thread count to be applied to the plurality of graphics compute units to execute the stream of instructions;
analyze the graphics program to be executed on the general purpose graphics processor at compile time to determine a set of latency parameters associated with the execution of the stream of instructions at the first hardware thread count; and
select a latency management technique to be implemented by the general purpose graphics processor based at least in part on the set of latency parameters associated with instruction sets implemented to execute the program:
determine the set of latency parameters associated with instruction count;
determine a composite latency score for the program from the set of latency parameters at the current thread count; and
compare the composite latency score at the current hardware thread count to a threshold.

6. The electronic device of claim 5 further comprising processing circuitry to:
generate an instruction for the general purpose graphics processor to select a second hardware thread count, greater than the first hardware thread count.

7. The electronic device of claim 6 the processor to:
implement an alternate latency management technique in response to a determination that the program latency cannot be adequately addressed by adjusting a thread count allocated to the instruction sets implemented to execute the program.

8. The electronic device of claim 7 , the processor to:
generate an instruction for the general purpose graphics processor to enable out-of-order instruction scheduling for hardware executing the program.

9. The electronic device of claim 5 , the processor to:
set the hardware thread count for execution of the program to the current hardware thread when the composite latency score falls beneath the threshold.

Assignees

• Intel Corp

Inventors

• Schluessler Travis
• Venkatesh Abhishek
• Ould-Ahmed-Vall Elmoustapha
• Gierach John
• Bar On Tomer
• Burke Devan

Classifications

• G06F8/4441

  Reducing the execution time required by the program code · CPC title

• G06F8/441

  Register allocation; Assignment of physical memory space to logical memory space · CPC title

• G06F11/3636 Primary

  by tracing the execution of the program · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F8/4452

  Software pipelining · CPC title