Virtual FPGA management and optimization system

Patent metadata

Field	Value
Publication number	US-10164639-B1
Application number	US-201715812411-A
Country	US
Kind code	B1
Filing date	Nov 14, 2017
Priority date	Nov 14, 2017
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

A macro scheduler includes a resource tracking module configured to update a database enumerating a plurality of macro components of a set of field programmable gate array (FPGA) devices, a communication interface configured to receive from a first client device a first design definition indicating one or more specified macro components for a design, resource allocation logic configured to allocate a first set of macro components for the design by allocating one of the plurality of macro components for each of the one or more specified macro components indicated in the first design definition, and configuration logic configured to implement the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition.

First claim

What is claimed is:

1. A macro scheduler, comprising:
a resource tracking module configured to update a database enumerating a plurality of macro components of a set of field programmable gate array (FPGA) devices;
a communication interface configured to receive from a first client device a first design definition indicating one or more specified macro components for a design;
resource allocation logic configured to allocate a first set of macro components for the design by allocating one of the plurality of macro components for each of the one or more specified macro components indicated in the first design definition; and
configuration logic configured to implement the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition.

2. The macro scheduler of claim 1 , wherein the first design definition comprises a macro graph defining connections between the one or more specified macro components and indicating a type of each of the one or more specified macro components.

3. The macro scheduler of claim 2 , wherein:
the one or more specified macro components comprise one or more specified tiles, one or more specified fixed function units, and one or more specified registers;
the first design definition further indicates a bitfile for each of the one or more specified tiles; and
for each specified tile of the one or more specified tiles, the configuration logic is configured to program an allocated tile in the first set of macro components based on the bitfile for the specified tile.

4. The macro scheduler of claim 1 , wherein the resource tracking module is further configured to associate each of the first set of macro components with a network address of the first client device and with a first task requested by the first client device.

5. The macro scheduler of claim 1 , wherein the resource tracking module is further configured to, for each macro component of the plurality of macro components, record in the database a location of the macro component in the set of FPGA devices and an availability of the macro component.

6. The macro scheduler of claim 1 , further comprising synthesis logic configured to:
during execution of a task in an initial configuration of the set of FPGA devices, wherein the initial configuration is indicated by the first design definition, generate an optimized configuration for the design, wherein the configuration logic is further configured to reprogram the set of FPGA devices to replace the initial configuration with the optimized configuration prior to restarting execution of the task in the optimized configuration of the set of FPGA devices; and
generate a remap notification correlating initial port locations in the initial configuration with optimized port locations in the optimized configuration.

7. The macro scheduler of claim 1 , wherein the first design definition comprises a definition for an accelerator, and wherein the resource allocation logic is further configured to:
schedule execution in the accelerator of a first task from the first client device during a first time period, and
schedule execution in the accelerator of a second task from a second client device during a second time period.

8. The macro scheduler of claim 1 , wherein the resource allocation logic is further configured to allocate a second set of the plurality of macro components for a second design defined by a second design definition received from a second client device, wherein a first subset of macro components in the first set of macro components is located in the same FPGA device of the set of FPGA devices as a second subset of macro components in the second set of macro components.

9. The macro scheduler of claim 1 , wherein the first set of macro components comprises macro components of at least two different FPGA devices of the plurality of FPGA devices.

10. A method, comprising:
updating a database enumerating a plurality of macro components of a set of field programmable gate array (FPGA) devices;
receiving from a first client device a first design definition indicating one or more specified macro components for a design;
allocating a first set of macro components for the design by allocating one of the plurality of macro components for each of the one or more specified macro components indicated in the first design definition; and
implementing the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition.

11. The method of claim 10 , wherein:
the one or more specified macro components comprise one or more specified tiles;
the first design definition further indicates a bitfile for each of the one or more specified tiles; and
the method further comprises:
for each specified tile of the one or more specified tiles, programming an allocated tile in the first set of macro components based on the bitfile for the specified tile.

12. The method of claim 10 , further comprising:
associating each of the first set of macro components with a network address of the first client device and with a first task requested by the first client device.

13. The method of claim 10 , further comprising:
for each macro component of the plurality of macro components, recording in the database a location of the macro component in the set of FPGA devices and an availability of the macro component.

14. The method of claim 10 , further comprising:
during execution of a task in an initial configuration of the set of FPGA devices, wherein the initial configuration is indicated by the first design definition, generating an optimized configuration for the design;
reprogramming the set of FPGA devices to replace the initial configuration with the optimized configuration prior to restarting execution of the task in the optimized configuration of the set of FPGA devices; and
generating a remap notification correlating initial port locations in the initial configuration with optimized port locations in the optimized configuration.

15. The method of claim 10 , wherein the first design definition comprises a definition for an accelerator, and wherein the method further comprises:
scheduling execution in the accelerator of a first task from the first client device during a first time period, and
scheduling execution in the accelerator of a second task from a second client device during a second time period.

16. The method of claim 10 , further comprising:
allocating a second set of the plurality of macro components for a second design defined by a second design definition received from a second client device, wherein a first subset of macro components in the first set of macro components is located in the same FPGA device of the set of FPGA devices as a second subset of macro components in the second set of macro components.

17. A system, comprising:
a set of field programmable gate array (FPGA) devices comprising a plurality of macro components;
a database configured to enumerate the plurality of macro components; and
a standalone macro scheduler, comprising:
a resource tracking module configured to update the database;
a communication interface configured to receive from a first client device a first design definition indicating one or more specified macro components for a design;
resource allocation logic configured to allocate a first set of macro components for the design by allocating one of the plurality of macro components for each of the one or more specified macro components indicated in the first

Assignees

• Advanced Micro Devices Inc

Inventors

• Roberts David A
• Kegel Andrew G
• Mednick Elliot H

Classifications

• G06F9/5011

  the resources being hardware resources other than CPUs, Servers and Terminals · CPC title

• G06F9/5077

  Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455) · CPC title

• H03K19/1776

  for memories · CPC title

• G06F30/34

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F9/4843

  by program, e.g. task dispatcher, supervisor, operating system · CPC title