Scan data control apparatus and electronic system having the same

Patent metadata

Field	Value
Publication number	US-10539616-B2
Application number	US-201715680109-A
Country	US
Kind code	B2
Filing date	Aug 17, 2017
Priority date	Dec 22, 2016
Publication date	Jan 21, 2020
Grant date	Jan 21, 2020

Abstract

A scan data control apparatus includes a trigger circuit, a scan sequencer, a shift register, and a transmitter. The trigger circuit is configured to receive a trigger signal, detect a malfunction of a system and output a scan mode start signal and a scan mode end signal. The scan sequencer is configured to output scan enable signals corresponding to a CPU and a master to the CPU and the master. The shift register is configured to receive scan data of the CPU and the master from the CPU and the master. The transmitter is configured to receive the scan data of the CPU and the master and output the scan data to a memory.

First claim

What is claimed is:

1. A scan data control apparatus comprising:
a trigger circuit configured to receive a trigger signal, detect a malfunction of a system in response to the trigger signal;
a scan sequencer circuit configured to output, in response to the trigger circuit detecting the malfunction, scan enable signals corresponding to a central processing unit (CPU) and a master device to the CPU and the master device, respectively;
a shift register configured to receive, in response to a scan clock signal received from the scan sequencer circuit, scan data of the CPU and the master device from the CPU and the master device, respectively; and
a transmitter circuit configured to receive, from the shift register, the scan data of the CPU and the master device and output the scan data for storage within a memory, wherein
the trigger circuit outputs a scan mode end signal in response to the storage of the scan data within the memory being completed.

2. The scan data control apparatus of claim 1 , further comprising a special function register configured to output, to the transmitter circuit, an address within the memory for storing the scan data of the CPU and the master device.

3. The scan data control apparatus of claim 2 , wherein the special function register is configured to output a scan mode enable signal, to the trigger circuit, that indicates whether a scan mode exists or not.

4. The scan data control apparatus of claim 2 , wherein:
the special function register is configured to output a masking signal to the scan sequencer circuit, and
the masking signal indicates whether each of the CPU and the master device will output the scan data.

5. The scan data control apparatus of claim 1 , wherein:
when the trigger signal is inputted to the trigger circuit, the trigger circuit determines that a scan mode has an enabled status,
when the scan mode has the enabled status, the trigger circuit outputs a scan mode start signal, and
when the scan mode has a disabled status, the trigger circuit outputs a system reset signal.

6. The scan data control apparatus of claim 1 , wherein the scan sequencer circuit is configured to output a scan clock signal to the CPU, the master device, and the shift register.

7. An electronic system comprising:
a bus configured to transmit data;
a memory configured to store the data;
a central processing unit (CPU) and a master device which are connected to the bus;
a power management circuit connected to the bus and configured to provide power to the CPU and the master device;
a memory interface connected to the bus and configured to control an operation of the memory; and
a scan data control circuit configured to detect a malfunction of a system and store scan data of the CPU and the master device within the memory, wherein the scan data control circuit comprises:
a trigger circuit configured to detect the malfunction of the system;
a scan sequencer circuit configured to output, in response to the trigger circuit detecting the malfunction, scan enable signals corresponding to the CPU and the master device to the CPU and the master device, respectively;
a shift register configured to receive the scan data of the CPU and the master device from the CPU and the master device, respectively; and
a transmitter circuit configured to receive the scan data of the CPU and the master device from the shift register and output the scan data to the memory, wherein

the trigger circuit outputs a scan mode end signal in response to storage of the scan data within the memory being completed.

8. The electronic system of claim 7 , wherein:
the scan data control circuit further comprises a special function register configured to: (1) output, to the transmitter circuit, an address within the memory for storing the scan data of the CPU and the master device, (2) output, to the trigger circuit, a scan mode enable signal indicating whether a scan mode exists or not, and (3) output a masking signal to the scan sequencer circuit, and
the masking signal indicates whether each of the CPU and the master device will output the scan data.

9. The electronic system of claim 8 , further comprising software configured to preset the scan mode enable signal and the masking signal within the special function register and read the scan data from the memory.

10. The electronic system of claim 7 , wherein the power management circuit is configured to output a clock stop request signal to the CPU and the master device to stop a clock signal of the CPU and the master device.

11. The electronic system of claim 7 , wherein the power management circuit is configured to output a reset isolation request signal to the CPU and the master device to selectively reset the CPU and the master device.

12. The electronic system of claim 7 , wherein the power management circuit is configured to output a bus and memory initialization request signal to the bus and the memory to initialize the bus and the memory.

13. The electronic system of claim 7 , wherein:
the power management circuit is configured to receive a scan mode end signal and reset the electronic system, excluding the memory, and
the memory is excluded from being reset to prevent deletion of the scan data stored in the memory.

14. The electronic system of claim 7 , further comprising an internal memory directly connected to the bus and disposed in a system-on-chip.

15. A system on chip comprising:
a scan control circuit that detects a system malfunction and communicates a scan mode start signal in response to detecting the system malfunction;
a power management circuit that communicates a scan request signal to a processor in response to receiving the scan mode start signal from the scan control circuit; and
the processor that communicates, in response to a scan enable signal received from the scan control circuit, scan data to the scan control circuit for storage in a memory device.

16. The system on chip of claim 15 , wherein the processor communicates the scan data to the scan control circuit in synchronization with a clock signal generated by the scan control circuit.

17. The system on chip of claim 15 , wherein the scan control circuit stores the scan data received from the processor in a predetermined address of the memory device, which predetermined address is stored within a register of the scan control circuit.

18. The system on chip of claim 15 , wherein the power management circuit communicates, in response to receiving the scan mode start signal from the scan control circuit, a request for the processor to discontinue a clock signal generated by the processor.

19. The system on chip of claim 15 , wherein the power management circuit communicates, in response to receiving the scan mode start signal from the scan control circuit, a request for the processor to reset its operation and a request for the memory device to initialize its operation.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeong Kyoung-Heon
• Kim Ho-Sung
• Lee Sung-Jae

Classifications

• G01R31/318544 Primary

  Scanning methods, algorithms and patterns (G01R31/3183 takes precedence) · CPC title

• G01R31/318513

  Test of Multi-Chip-Moduls · CPC title

• G01R31/31705

  Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits (generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544) · CPC title

• G01R31/318555

  Control logic · CPC title

• G01R31/31725 Primary

  Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937) · CPC title