Apparatus and system of a level shifter

Patent metadata

Field	Value
Publication number	US-10536148-B2
Application number	US-201715800651-A
Country	US
Kind code	B2
Filing date	Nov 1, 2017
Priority date	Nov 1, 2017
Publication date	Jan 14, 2020
Grant date	Jan 14, 2020

Abstract

Some demonstrative embodiments include a level shifter to shift a high logic level and a low logic level of a Direct Current (DC) control signal of a first voltage domain to a high logic level and a low logic level of a second voltage domain, respectively.

First claim

What is claimed is:

1. A level shifter to shift a high logic level and a low logic level of a Direct Current (DC) control signal of a first voltage domain to a high logic level and a low logic level of a second voltage domain, respectively, the level shifter comprising:
a pulse generator configured to generate a set pulse signal when the DC control signal shifts from the low logic level of the first voltage domain to the high logic level of the first voltage domain, and to generate a reset pulse signal when the DC control signal shifts from the high logic level of the first voltage domain to the low logic level of the first voltage domain, the set pulse signal to create a first voltage drop between a first node and a second node, the reset pulse signal to create a second voltage drop between the first node and the second node;
a first shifting transistor configured to create the first voltage drop based on the set pulse signal, a drain of the first shifting transistor is connected to the first node;
a second shifting transistor configured to create the second voltage drop based on the reset pulse signal, a drain of the second shifting transistor is connected to the second node;
a first control transistor to trigger a set voltage based on the first voltage drop, a gate of the first control transistor is connected to the first node;
a second control transistor to trigger a reset voltage based on the second voltage drop, a gate of the second control transistor is connected to the second node; and
a set/reset (SR) latch coupled between a first supply voltage and a second supply voltage corresponding to the second voltage domain, the SR latch configured to output the high logic level of the second voltage domain based on the set voltage, and to output the low logic level of the second voltage domain based on the reset voltage.

2. The level shifter of claim 1 , wherein the first control transistor comprises a drain coupled to a set input of the SR latch, and a source coupled to the second node, the second control transistor comprising a drain coupled to a reset input of the SR latch, and a source coupled to the first node.

3. The level shifter of claim 1 , wherein the first voltage drop is configured to open the gate of the first control transistor and to close the gate of the second control transistor, the second voltage drop is configured to open the gate of the second control transistor and to close the gate of the first control transistor.

4. The level shifter of claim 1 , wherein a value of the first voltage drop is opposite to a value of the second voltage drop.

5. The level shifter of claim 1 , wherein an absolute value of the first voltage drop is greater than a threshold voltage of the first control transistor, and an absolute value of the second voltage drop is greater than a threshold voltage of the second control transistor.

6. The level shifter of claim 1 , wherein the first control transistor comprises a drain connected to a set input of the SR latch, and a source connected to the second node, wherein the second control transistor comprises a drain connected to a reset input of the SR latch, and a source connected to the first node, and wherein the first voltage drop is configured to open the gate of the first control transistor and to close the gate of the second control transistor, and the second voltage drop is configured to open the gate of the second control transistor and to close the gate of the first control transistor.

7. The level shifter of claim 1 , wherein each of the first and second shifting transistors comprises an N-channel transistor.

8. The level shifter of claim 1 comprising a first load resistor and a second load resistor coupled to the first supply voltage, the first load resistor coupled to the first node, the second load resistor coupled to the second node, the first voltage drop comprises a first voltage drop between the first and second load resistors, and the second voltage drop comprises a second voltage drop between the first and second load resistors.

9. The level shifter of claim 8 , wherein a resistance of the first load resistor is equal to a resistance of the second load resistor.

10. The level shifter of claim 1 comprising a first resistor and a second resistor coupled to the second supply voltage corresponding to the second voltage domain, the set voltage is across the first resistor, and the reset voltage is across the second resistor.

11. The level shifter of claim 10 , wherein the first resistor is coupled to a drain of the first control transistor and to a set input of the SR latch, the second resistor is coupled to a drain of the second control transistor and to a reset input of the SR latch.

12. The level shifter of claim 1 , wherein the SR latch is configured to output the high logic level of the second voltage domain when the set voltage is at a set input of the SR latch, and to output the low logic level of the second voltage domain when the reset voltage is at a reset input of the SR latch.

13. The level shifter of claim 1 comprising a high-side level shifter.

14. The level shifter of claim 1 , wherein the high logic level of the first voltage domain comprises a drain-drain voltage (VDD), the low logic level of the first voltage domain comprising a ground (GND), the high logic level of the second voltage domain comprises a BOOT voltage, and the low logic level of the second voltage domain comprising an LX voltage.

15. The level shifter of claim 1 , wherein each of the first and second control transistors comprises a P-channel transistor.

16. The level shifter of claim 1 comprising a low-side level shifter.

17. The level shifter of claim 1 , wherein the high logic level of the first voltage domain comprises a BOOT voltage, the low logic level of the first voltage domain comprising an LX voltage, the high logic level of the second voltage domain comprises a drain-drain voltage (VDD), and the low logic level of the first voltage domain comprising a ground (GND).

18. The level shifter of claim 1 , wherein each of the first and second control transistors comprises an N-channel transistor.

19. An electronic device comprising:
electronic circuitry to generate a Direct Current (DC) control signal; and
a DC to DC (DC-DC) converter to convert logic levels of the DC control signal from a first voltage domain to a second voltage domain, the DC-DC converter comprising:
a level shifter to shift a high logic level and a low logic level of the DC control signal from the first voltage domain to a high logic level and a low logic level of the second voltage domain, respectively, the level shifter comprising:
a pulse generator configured to generate a set pulse signal when the DC control signal shifts from the low logic level of the first voltage domain to the high logic level of the first voltage domain, and to generate a reset pulse signal when the DC control signal shifts from the high logic level of the first voltage domain to the low logic level of the first voltage domain, the set pulse signal to create a first voltage drop between a first node and a second node, and the reset pulse signal to create a second voltage drop between the first node and the second node;
a first control transistor to trigger a set voltage based on the first voltage drop, a gate of the first control transistor is connected to the first node;
a second control transistor to trigger a reset voltage based on the second voltage drop, a gate of the second control transistor is connected to the second node; and
a set/reset (SR)

Assignees

• Tower Semiconductor Ltd

Inventors

• Lerner Valentin
• Pollak Dan

Classifications

• H03K19/018521 Primary

  of complementary type, e.g. CMOS · CPC title