Package structure and method for forming the same

Patent metadata

Field	Value
Publication number	US-10535609-B2
Application number	US-201816020030-A
Country	US
Kind code	B2
Filing date	Jun 27, 2018
Priority date	Nov 10, 2016
Publication date	Jan 14, 2020
Grant date	Jan 14, 2020

Abstract

Package structures and methods for forming the same are provided. A package structure includes a package layer. The package structure also includes an integrated circuit die and a first connector embedded in the package layer. The package structure further includes a redistribution layer over the package layer. The integrated circuit die is electrically connected to the redistribution layer through the first connector. In addition, the package structure includes a passivation layer over the redistribution layer. The package structure also includes a second connector over the passivation layer. A first portion of the redistribution layer and a second portion of the second connector extend into the passivation layer. The second portion of the second connector has a tapered profile along a direction from the integrated circuit die towards the first connector.

First claim

What is claimed is:

1. A package structure, comprising:
a package layer;
an integrated circuit die and a first connector embedded in the package layer;
a redistribution layer over the package layer, wherein the integrated circuit die is electrically connected to the redistribution layer through the first connector;
a passivation layer over the redistribution layer; and
a second connector over the passivation layer, wherein a first portion of the redistribution layer and a second portion of the second connector extend into the passivation layer, and wherein the second portion of the second connector covers an upper portion of a slope sidewall of the passivation layer, and the first portion of the redistribution layer covers a lower portion of the slope sidewall of the passivation layer, wherein the slope sidewall of the passivation layer has a tapered profile along a direction from the integrated circuit die towards the first connector.

2. The package structure as claimed in claim 1 , wherein the second connector comprises an under bump metallurgy layer and a bump over the under bump metallurgy layer, and wherein the passivation layer has a top surface facing the second connector, and a bottom surface of the bump is lower than the top surface of the passivation layer.

3. The package structure as claimed in claim 1 , further comprising:
a second package layer, wherein a sidewall of the integrated circuit die adjoins the package layer and the second package layer, and the package layer and the integrated circuit die are embedded in the second package layer, and wherein the package layer comprises first fillers having a first size, and the second package layer comprises second fillers having a second size that is greater than the first size.

4. The package structure as claimed in claim 3 , further comprising:
a third package layer, wherein the second package layer has a portion between the third package layer and the integrated circuit die, wherein the third package layer comprises third fillers having a third size that is greater than the second size.

5. The package structure as claimed in claim 1 , further comprising:
a second package layer covering an edge of the passivation layer and a first sidewall of the package layer, wherein the edge of the passivation layer is between the first sidewall of the package layer and a second sidewall of the second package layer from a top view.

6. A package structure, comprising:
a package layer;
an integrated circuit die embedded in the package layer, wherein the integrated circuit die has an active surface and a non-active surface;
a bump embedded in the package layer, wherein the bump is coupled to the active surface;
a redistribution layer over the package layer, wherein the integrated circuit die is electrically connected to the redistribution layer through the bump;
a passivation layer over the redistribution layer; and
a connector over the passivation layer, wherein a first portion of the redistribution layer and a second portion of the connector extend into the passivation layer and contact with each other, and wherein the first portion of the redistribution layer and the second portion of the connector gradually shrink along a direction from the non-active surface toward the active surface to form a slope sidewall.

7. The package structure as claimed in claim 6 , wherein there is an interface between the first and second portions in the passivation layer, and wherein the passivation layer has a first surface, which faces the integrated circuit die, and a second surface, which is opposite to the first surface and is closer to the interface than the first surface.

8. The package structure as claimed in claim 7 , wherein the redistribution layer comprises a conductive layer and a seed layer between the conductive layer and the passivation layer, and wherein the conductive layer and the seed layer extend along the first surface into the passivation layer to electrically connect to the connector.

9. The package structure as claimed in claim 8 , wherein the connector comprises a second bump and a second seed layer between the second bump and the passivation layer, and wherein the second seed layer extends along the second surface into the passivation layer and adjoins the conductive layer and the seed layer.

10. The package structure as claimed in claim 9 , wherein the second bump is separated from the conductive layer and the seed layer by the second seed layer.

11. The package structure as claimed in claim 6 , further comprising a second package layer, wherein the package layer has a portion between the second package layer and the non-active surface.

12. The package structure as claimed in claim 11 , wherein the package layer comprises first fillers having a first size, and the second package layer comprises second fillers having a second size that is greater than the first size.

13. A package structure, comprising:
a package layer;
an integrated circuit die and a bump embedded in the package layer;
a redistribution layer over the package layer, wherein the integrated circuit die is electrically connected to the redistribution layer through the bump;
a passivation layer over the redistribution layer, wherein a first portion of the redistribution layer extends into the passivation layer, and the passivation layer comprises a sidewall adjoining the first portion of the redistribution layer; and
a connector over the passivation layer, wherein a second portion of the connector extends into the passivation layer to electrically connect to the redistribution layer, and there is an acute angle between the sidewall of the passivation layer and a first surface of the passivation layer facing the connector, wherein a lateral sidewall of the first portion of the redistribution layer and a lateral sidewall of the second portion of the connector are substantially coplanar in the passivation layer and are inclined at the acute angle.

14. The package structure as claimed in claim 13 , wherein the passivation layer has a second surface opposite to the first surface, the redistribution layer extends along the second surface into the passivation layer, and the first portion of the redistribution layer gradually shrinks along a direction from the second surface to the first surface.

15. The package structure as claimed in claim 13 , wherein the passivation layer has a second surface opposite to the first surface, the connector extends along the first surface into the passivation layer, and the second portion of the connector gradually shrinks along a direction from the second surface to the first surface.

16. The package structure as claimed in claim 13 , wherein the redistribution layer comprises a conductive layer and a seed layer between the conductive layer and the passivation layer, and wherein the connector comprises a second bump and a second seed layer between the second bump and the passivation layer, and a portion of the second seed layer is sandwiched between the second bump and the conductive layer.

17. The package structure as claimed in claim 16 , wherein the sidewall of the passivation layer is covered by the seed layer and the second seed layer.

18. The package structure as claimed in claim 16 , wherein the conductive layer and the second bump is separated from the passivation layer by the seed layer and the second seed layer.

19. The package structure as claimed in claim 1 , wherein a lateral sidewall of the first portion of the redistribution layer and a lateral sidewall of the secon

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Yi-Da
• Lin Cheng-Ping
• Lin Wei-Hung
• Lin Chih-Wei
• Cheng Ming-Da
• Hsieh Ching-Hua
• Liu Chung-Shi

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/0198

  batch processes · CPC title