Semiconductor device and method of manufacture

Patent metadata

Field	Value
Publication number	US-10535566-B2
Application number	US-201715420280-A
Country	US
Kind code	B2
Filing date	Jan 31, 2017
Priority date	Apr 28, 2016
Publication date	Jan 14, 2020
Grant date	Jan 14, 2020

Abstract

A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a dielectric layer over a semiconductor substrate;
patterning a photoresist over the dielectric layer;
placing the semiconductor substrate and the photoresist into an etching chamber;
transferring the pattern of the photoresist to the dielectric layer to expose an external connector, the external connector being located further from the semiconductor substrate than any metallization line of the semiconductor device, the transferring using a reactive ion etching process, wherein the transferring the pattern of the photoresist creates reaction by-products which remain on the semiconductor substrate after the transferring the pattern; and
removing the photoresist from the dielectric layer prior to removing the photoresist from the etching chamber, wherein the removing the photoresist also removes the reaction by-products, wherein the removing the photoresist further comprises:
a pre-heating removal step with a first set of process conditions;
a stabilization ashing step with a second set of process conditions different from the first set of process conditions; and
a stripping step with a third set of process conditions different from the first set of process conditions and different from the second set of process condition, the stripping step removing both the photoresist as well as the reaction by-products.

2. The method of claim 1 , wherein the removing the photoresist comprises exposing the photoresist to oxygen.

3. The method of claim 1 , wherein the semiconductor substrate comprises semiconductor fins.

4. The method of claim 1 , wherein the etching process further comprises:
a main etching process; and
an overetching process.

5. The method of claim 1 , wherein the dielectric layer further comprises:
a first dielectric material; and
a second dielectric material over the first dielectric material, wherein the second dielectric material is different from the first dielectric material.

6. The method of claim 5 , wherein the first dielectric material is undoped silicate glass and the second dielectric material is silicon nitride.

7. The method of claim 5 , wherein the dielectric layer is located over a first passivation layer.

8. A method of manufacturing a semiconductor device, the method comprising:
depositing a photoresist onto a dielectric material over a substrate;
patterning the photoresist;
etching the dielectric material through the photoresist, wherein the etching the dielectric material uses a reactive ion etching process with oxygen from a first source of oxygen as at least one reactant; and
removing the photoresist after the etching the dielectric material, wherein the removing the photoresist uses oxygen from the first source of oxygen, the removing the photoresist further comprising:
a pre-heating removal step with a first set of process conditions;
a stabilization ashing step with a second set of process conditions different from the first set of process conditions; and
a stripping step with a third set of process conditions different from the first set of process conditions and different from the second set of process condition, the stripping step removing both the photoresist as well as by-products of the etching the dielectric material.

9. The method of claim 8 , wherein the etching the dielectric material and the removing the photoresist are performed in the same etching chamber.

10. The method of claim 8 , wherein the etching the dielectric material etches a layer of silicon nitride and a layer of undoped silicon oxide.

11. The method of claim 8 , wherein the etching the dielectric material further comprises etching a capping layer between the dielectric material and a conductive region.

12. The method of claim 8 , wherein the depositing the photoresist onto the dielectric material over the substrate deposits the photoresist over FinFET devices.

13. The method of claim 8 , wherein the removing the photoresist uses only oxygen to remove the photoresist.

14. The method of claim 13 , wherein the removing the photoresist is performed at an oxygen flow rate of less than 1000 sccm.

15. A method of manufacturing a semiconductor device, the method comprising:
patterning a photoresist to expose a dielectric material over a top metallization layer and form a patterned photoresist, wherein the top metallization layer is separated from a semiconductor substrate by each other metallization layer of the semiconductor device, and wherein a first portion of the top metallization layer has a sidewall aligned with a dielectric material, a second portion of the top metallization layer being embedded within the dielectric material;
dry etching the dielectric material through the patterned photoresist, wherein the dry etching the dielectric material utilizes a plasma process;
directly after the dry etching the dielectric material, performing a liner removal process; and
directly after the liner removal process, ashing the photoresist, wherein the ashing the photoresist further removes by-products from the dry etching the dielectric material and wherein the dry etching, the liner removal process, and the ashing are performed within a single etching chamber.

16. The method of claim 15 , wherein the dielectric material is located over FinFET devices.

17. The method of claim 15 , wherein the ashing the photoresist comprises exposing the photoresist to oxygen without other etchants.

18. The method of claim 17 , wherein the oxygen is flowed into the single etching chamber at a flow rate of less than 1000 sccm.

19. The method of claim 15 , wherein the ashing the photoresist comprises exposing the photoresist to oxygen and nitrogen.

20. The method of claim 19 , wherein the ashing the photoresist further comprises exposing the photoresist to argon at the same time as the oxygen and nitrogen.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Hung-Hao
• Chang Che-Cheng
• Tseng Horng-Huei
• Chen Wen-Tung
• Liu Yu-Cheng

Classifications

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/01938

  in gaseous form, e.g. by CVD or PVD · CPC title