Vertical hall-effect sensor for detecting two-dimensional in-plane magnetic fields

Patent metadata

Field	Value
Publication number	US-10534045-B2
Application number	US-201715709866-A
Country	US
Kind code	B2
Filing date	Sep 20, 2017
Priority date	Sep 20, 2017
Publication date	Jan 14, 2020
Grant date	Jan 14, 2020

Abstract

A microelectronic device includes a vertical Hall sensor for measuring magnetic fields in two dimensions. In one implementation, the disclosed microelectronic device involves a vertical Hall plate with a cross-shaped upper terminal and a lower terminal which includes a buried layer. The cross-shaped upper terminal has a length-to-width ratio of 5 to 12 where it contacts the vertical Hall plate. The length is measured from one end of one arm of the cross-shaped upper terminal to an opposite end of an opposite arm. The width is an average width of both arms. Hall sense taps are located outside of the cross-shaped upper terminal. Current returns connect to the buried layer.

First claim

What is claimed is:

1. A microelectronic device, comprising:
a substrate;
a two-dimensional (2D) vertical Hall cell, comprising:
a vertical Hall plate in the substrate;
a cross-shaped upper terminal contacting a top of the vertical Hall plate;
a buried layer contacting a bottom of the vertical hall plate;
Hall sense taps outside the cross-shaped upper terminal, the Hall sense taps being electrically coupled to the vertical Hall plate; and
current return regions in the substrate outside of the vertical Hall plate, the current return regions comprising semiconductor material having a same conductivity type as the buried layer, the current return regions being electrically coupled to the buried layer, wherein the current return regions extend upward from the buried layer toward a top surface of the substrate.

2. The microelectronic device of claim 1 , wherein the cross-shaped upper terminal includes an upper contact region including n-type semiconductor material.

3. The microelectronic device of claim 2 , wherein the upper contact region has an average electrical conductivity at least 100 times greater than an average electrical conductivity of the vertical Hall plate.

4. The microelectronic device of claim 3 , wherein an average dopant density of the n-type semiconductor material in the upper contact region is 5×10 18 cm −3 to 5×10 20 cm −3 .

5. The microelectronic device of claim 1 , wherein the cross-shaped upper terminal includes metal silicide.

6. The microelectronic device of claim 1 , further comprising contacts on the cross-shaped upper terminal, wherein the contacts extend to ends of the cross-shaped upper terminal.

7. The microelectronic device of claim 1 , further comprising a cross-shaped contact on the cross-shaped upper terminal.

8. The microelectronic device of claim 1 , wherein the buried layer includes n-type semiconductor material having an average dopant density at least 10 times greater than an average dopant density of the vertical Hall plate.

9. The microelectronic device of claim 1 , wherein the Hall sense taps are electrically coupled to the vertical Hall plate at a vertical location closer to the buried layer than to a top surface of the substrate.

10. The microelectronic device of claim 1 , wherein the current return regions have a dopant distribution similar to a dopant distribution of the vertical Hall plate.

11. The microelectronic device of claim 1 , wherein the current return regions have an average dopant density at least 10 times greater than an average dopant density of the vertical Hall plate.

12. The microelectronic device of claim 1 , wherein the current return regions are laterally isolated from the vertical Hall plate by semiconductor material having an opposite conductivity type from the current returns.

13. The microelectronic device of claim 1 , wherein the current return regions are laterally isolated from the vertical Hall plate by a deep trench including dielectric material, the deep trench extending to the buried layer.

14. The device of claim 1 , wherein the cross-shaped upper terminal has a length-to-width ratio of 5 to 12 where it contacts the vertical Hall plate, the length being measured from an end of a first arm of the cross-shaped upper terminal to an opposite end of a second, opposite, arm of the cross-shaped upper terminal, the width being an average width of the first arm and the second arm.

15. A method, comprising:
providing a substrate which includes a semiconductor material;
forming a buried layer in the substrate;
forming a vertical Hall plate in the substrate on the buried layer;
forming Hall sense taps outside of the cross-shaped upper terminal; and
current return regions in the substrate outside of the Hall sense taps, the current return regions extending from the buried layer upward toward a top surface of the substrate, wherein the current return regions are laterally separated from the vertical Hall plate.

16. The method of claim 15 , wherein forming the cross-shaped upper terminal includes forming an upper contact region having a cross shape contacting the vertical Hall plate, wherein the upper contact region has a same conductivity type as the vertical Hall plate, and the upper contact region has an average dopant density at least 100 times greater than an average dopant density of the vertical Hall plate.

17. The method of claim 16 , wherein forming the cross-shaped upper terminal includes forming metal silicide on the upper contact region.

18. The method of claim 15 , further comprising forming a cross-shaped contact on the cross-shaped upper terminal.

19. The method of claim 15 , wherein the vertical Hall plate includes n-type semiconductor material.

20. The method of claim 15 , further comprising forming a cross-shaped upper terminal on the vertical hall plate, wherein the cross-shaped upper terminal has a length-to-width ratio of 5 to 12 where it contacts the vertical Hall plate, the length being measured from an end of a first arm of the cross-shaped upper terminal to an opposite end of a second, opposite, arm of the cross-shaped upper terminal, the width being an average width of the first arm and the second arm.

Assignees

• Texas Instruments Inc

Inventors

• Green Keith Ryan
• Shulver Byron Jon Roderick
• Mirgorodski Iouri

Classifications

• G01R33/0005

  Geometrical arrangement of magnetic sensor elements; Apparatus combining different magnetic sensor types (G01R33/0206 takes precedence) · CPC title

• G01R33/077 Primary

  Vertical Hall-effect devices · CPC title

• G01R33/0052

  Manufacturing aspects; Manufacturing of single devices, i.e. of semiconductor magnetic sensor chips (devices based on galvano-magnetic effect or the like H10N50/85) · CPC title

• G01D5/145

  influenced by the relative movement between the Hall device and magnetic fields (see G01R33/06) · CPC title

• H01L43/14

  Electricity · mapped topic