Systems and methods for replaceable bail grid array (BGA) packages on board substrates

Patent metadata

Field	Value
Publication number	US-10531575-B2
Application number	US-201616072367-A
Country	US
Kind code	B2
Filing date	Apr 1, 2016
Priority date	Apr 1, 2016
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

The systems and methods described herein are directed to using a plurality of interface elements (e.g., sockets) and/or stud-bump elements embedded into board substrates (e.g., a motherboard) to enable the interchange of variable configuration components (e.g., electronic components, chips, and the like) that are mounted on package substrates having ball grid arrays (BGAs). In some aspects, this interchange can be accomplished while leaving the pre-existing board substrate design and various peripheral system components of the board substrate unchanged.

First claim

What is claimed:

1. A board substrate, comprising:
a blind via fabricated in the board substrate, the blind via having a pre-determined diameter, depth, and, pitch; and
an interface element fabricated in the blind via, the interface element further comprising a base structure, the base structure comprising one or more conductive sidewalls and a conductive bottom portion, wherein a ball of a ball grid array (BGA) is in contact with at least the conductive bottom portion.

2. The board substrate of claim 1 , wherein the conductive bottom portion further comprises a stud bump element.

3. The board substrate of claim 2 , the stud bump element comprises a metallic, semi-metallic, or intermetallic material.

4. The board substrate of claim 1 , wherein the base structure is plated into the board substrate.

5. The board substrate of claim 1 , wherein the base structure is deposited through one or more of a sputtering technique, a paste printing, squeegee, an atomic layer deposition (ALD) technique, or a physical vapor deposition (PVD) technique.

6. The board substrate of claim 1 , wherein the base structure comprises a metallic, semi-metallic, or intermetallic material.

7. The board substrate of claim 1 , wherein the base structure comprises a surface finish.

8. The board substrate of claim 7 , wherein the surface finish comprises an electroless nickel immersion gold (ENIG) or electroless nickel electroless palladium immersion gold (ENIPIG).

9. A method of fabricating a board substrate, comprising:
forming a blind via in the board substrate, the blind via having a pre-determined diameter, depth, and pitch;
fabricating an interface element in the blind via, the interface element further comprising a base structure, the base structure comprising one or more conductive sidewalls and a conductive bottom portion;
aligning a package substrate comprising the BGA with the board substrate; and
applying an enabling load of a pre-determined magnitude to the package substrate or board substrate for attaching the package substrate to the board substrate using the interface element, wherein, based on the enabling load, a ball of a ball grid array (BGA) is in contact with at least the conductive bottom portion.

10. The method of claim 9 , wherein forming the blind via in the board substrate further comprises drilling a blind via in the board substrate.

11. The method of claim 9 , wherein the method further comprises masking a portion of a surface of the board substrate, wherein the surface of the board that is covered excludes the blind via.

12. The method of claim 9 , wherein fabricating the interface element further comprises fabricating a stud bump element on the base structure wherein the stud bump element forms an additional contact surface with the BGA.

13. The method of claim 12 , wherein the method further comprises disposing the stud bump element using a pick and place system.

14. The method of claim 12 , wherein the stud bump element comprises a metallic, semi-metallic, or intermetallic material.

15. The method of claim 12 , wherein fabricating the stud bump element further comprises attaching a wire bond ball at a base of of the blind via.

16. The method of claim 9 , wherein the base structure is plated into the board substrate.

17. The method of claim 9 , wherein the base structure is deposited through one or more of a sputtering technique, a paste printing, squeegee, an atomic layer deposition (ALD) technique, or a physical vapor deposition (PVD) technique.

18. The method of claim 9 , wherein the method further comprises applying a surface finish to the base structure.

19. The method of claim 18 , wherein the surface finish comprises an electroless nickel immersion gold (ENIG) or electroless nickel electroless palladium immersion gold (ENIPIG).

20. The method of claim 9 , wherein the method further comprises applying a removing force of a pre-determined magnitude to the package substrate or board substrate for removing the package substrate or the board substrate.

Assignees

• Intel Corp

Inventors

• Sane Sandeep
• Swettlen Timothy

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W78/00

  Detachable holders for supporting packaged chips in operation · CPC title

• H05K2201/0367

  Metallic bump or raised conductor not used as solder bump · CPC title

• H05K3/3436

  having an array of bottom contacts, e.g. pad grid array or ball grid array components · CPC title