Connector with a housing and one or more groups of contacts for a computing system

US10530077B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10530077-B2
Application numberUS-201715807519-A
CountryUS
Kind codeB2
Filing dateNov 8, 2017
Priority dateNov 8, 2017
Publication dateJan 7, 2020
Grant dateJan 7, 2020

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  1. Title

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  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Embodiments of the present disclosure are directed towards a connector for a memory device in a computing system. In one embodiment, the connector includes a housing having a cavity to receive a mating end of a printed circuit board (PCB). The cavity includes first groups of first contacts arranged along an inside wall of the cavity, to engage with respective second groups of second contacts arranged around the mating end of the PCB. The cavity further includes a bar disposed inside the cavity to bridge the cavity, to receive a notch formed on the mating end of the PCB. A depth of the notch defines a number of the first groups of first contacts to be engaged with a respective number of the second groups of second contacts on the mating end of the PCB.

First claim

Opening claim text (preview).

What is claimed is: 1. A connector for a computing system, comprising: a housing having a cavity to receive a mating end of a printed circuit board (PCB), wherein the cavity includes: one or more first groups of first contacts arranged along an inside wall of the cavity, to engage with respective one or more second groups of second contacts arranged around the mating end of the PCB; and a bar disposed inside the cavity to bridge the cavity, to be received by a notch formed on the mating end of the PCB, wherein a depth of the notch defines a number of the first groups of first contacts to be engaged with a respective number of the second groups of second contacts on the mating end of the PCB. 2. The connector of claim 1 , wherein the first contacts comprise pins, and second contacts comprise pads or traces. 3. The connector of claim 1 , wherein the first contacts include: one or more shared contacts, common for the one or more first groups, to provide a power supply or grounding for the PCB; and a plurality of discrete signal contacts, to provide for data information exchange between the PCB and another component of the computing system. 4. The connector of claim 3 , wherein the one or more shared contacts are to further provide for a detection of an insertion of the PCB into the cavity. 5. The connector of claim 1 , wherein the one or more first groups comprise multiple rows of the first contacts, wherein the rows of the first contacts are disposed on the inside wall of the cavity adjacent each other, wherein the one or more second groups comprise at least one row of the second contacts, to engage a respective one of the multiple rows of first contacts in response to an insertion of the PCB into the cavity of the connector. 6. The connector of claim 5 , wherein each of the first groups comprises a row of the first contacts, and each of the second groups comprises a row of the second contacts. 7. The connector of claim 1 , wherein the bar comprises a key profile to mate a corresponding profile of the mating end of the PCB. 8. The connector of claim 7 , wherein the bar is disposed inside the cavity substantially perpendicularly to the inside wall of the cavity, wherein the bar comprises a substantially flat profile, wherein a plane that defines the profile of the bar is substantially perpendicular to a plane that defines the inside wall of the cavity. 9. The connector of claim 1 , wherein the PCB comprises an All Flash Array (AFA) solid state drive (SSD) memory device, wherein the connector comprises a Peripheral Component Interconnect Express (PCIe) bus, to connect the memory device with other components of the computing system, wherein the other components include a PCIe switch. 10. The connector of claim 1 , wherein the computing system comprises a data center or a server. 11. A computing system, comprising: a connector having a housing with a cavity, wherein the cavity includes one or more first groups of first contacts arranged along an inside wall of the cavity, and a bar disposed inside the cavity to bridge the cavity; and a printed circuit board (PCB) having a mating end insertable in the connector, wherein the mating end includes one or more second groups of second contacts arranged around the mating end, to engage respective one or more first groups of first contacts in response to an insertion of the PCB into the cavity of the connector, and a notch formed on the mating end of the PCB, to receive the bar in response to the insertion of the PCB into the cavity; wherein a depth of the notch defines a number of the first groups of first contacts to be engaged with a respective number of the one or more second groups of second contacts on the mating end of the PCB in response to the insertion of the PCB into the cavity. 12. The computing system of claim 11 , wherein the first contacts comprise pins, and the second contacts comprise pads or traces. 13. The computing system of claim 11 , wherein the one or more groups of first contacts includes: one or more shared contacts, common for the one or more first groups, to provide a power supply, or grounding for the PCB, or a detection of an insertion of the PCB inside the cavity; and a plurality of discrete signal contacts, to provide for data information exchange between the PCB and another component of the computing system. 14. The computing system of claim 11 , wherein the one or more first groups comprise multiple rows of the first contacts, wherein the rows of the first contacts are disposed on the inside wall of the cavity adjacent each other, wherein the one or more second groups comprise at least one row of the second contacts, to engage a respective one of the multiple rows of first contacts in response to an insertion of the PCB into the cavity of the connector. 15. The computing system of claim 11 , wherein the bar comprises a key profile to mate a corresponding profile of the mating end of the PCB, wherein the bar is disposed inside the cavity substantially perpendicularly to the inside wall of the cavity. 16. The computing system of claim 15 , wherein the PCB is to be inserted into the cavity substantially perpendicular to the bar, wherein the bar comprises a substantially flat profile, wherein a plane that defines the profile of the bar is substantially perpendicular to a plane that defines the inside wall of the cavity. 17. The computing system of claim 11 , wherein the computing system comprises a data center or a server, wherein the PCB comprises an All Flash Array (AFA) solid state drive (SSD) memory device, wherein the connector comprises a Peripheral Component Interconnect Express (PCIe) bus, to connect the memory device with other components of the computing system, wherein the other components include a PCIe switch.

Assignees

Inventors

Classifications

  • Notches between edge pads · CPC title

  • H05K1/117Primary

    Pads along the edge of rigid circuit boards, e.g. for pluggable connectors · CPC title

  • cooperating directly with the edge of the rigid printed circuits · CPC title

  • One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters (H05K1/142 and H05K1/147 take precedence) · CPC title

  • Mounting of expansion boards · CPC title

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Frequently asked questions

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What does patent US10530077B2 cover?
Embodiments of the present disclosure are directed towards a connector for a memory device in a computing system. In one embodiment, the connector includes a housing having a cavity to receive a mating end of a printed circuit board (PCB). The cavity includes first groups of first contacts arranged along an inside wall of the cavity, to engage with respective second groups of second contacts ar…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H05K1/117. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 07 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).