Extensible memory hub

US9396065B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9396065-B2
Application numberUS-201414314181-A
CountryUS
Kind codeB2
Filing dateJun 25, 2014
Priority dateJun 25, 2014
Publication dateJul 19, 2016
Grant dateJul 19, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure relates to an extensible memory hub. An apparatus may include a first extensible non-volatile memory (NVM) hub (EN hub). The first EN hub includes an upstream interface port configured to couple the first EN hub to an NVM controller or to a second EN hub; a downstream interface port configured to couple the first EN hub to a third EN hub or to a NVM device; at least one NVM device port, each NVM device port configured to couple the first EN hub to a respective NVM device via a NVM channel; and an EN hub controller. The EN hub controller includes command logic configured to initialize the first EN hub in response to an initialize chain command from the NVM controller, the initializing including enumerating each NVM device coupled to the first EN hub and each of one or more associated NVM dies.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus comprising: a first extensible non-volatile memory (NVM) hub (EN hub) comprising: an upstream interface port configured to couple the first EN hub to an NVM controller or to a second EN hub; a downstream interface port configured to couple the first EN hub to a third EN hub or to a NVM device; at least one NVM device port, each NVM device port configured to couple the first EN hub to a respective NVM device via a NVM channel; and an EN hub controller comprising command logic configured to initialize the first EN hub in response to an initialize chain command from the NVM controller, the initializing comprising to enumerate each NVM device coupled to the first EN hub and each of one or more associated NVM dies; wherein the command logic is further configured to identify a target NVM device for a memory access operation based, at least in part, on a target EN hub identifier, a target NVM device port identifier and a target volume address of the target NVM device. 2. The apparatus of claim 1 , wherein the command logic is configured to store a first EN hub identifier to the first EN hub; identify each NVM device coupled to the first EN hub at a respective NVM device port; assign for each NVM device, a volume address to each associated NVM die and associate each assigned volume address with the respective NVM device port; and provide a NVM device port identifier and associated one or more volume addresses to the NVM controller. 3. The apparatus of claim 1 , wherein the command logic is further configured to transmit a received command out the downstream interface port if the received command is not destined for the first EN hub. 4. The apparatus of claim 3 , wherein the EN hub controller further comprises a NVM timing generator and the command logic is further configured to regenerate the received command based, at least in part, on an output from the NVM timing generator. 5. The apparatus of claim 1 , wherein the EN hub controller further comprises ZQ calibration logic configured to perform ZQ calibration of a selected NVM device channel to couple a selected NVM device port and a selected NVM device and the command logic is configured to allow memory access operations to continue for one or more unselected NVM devices during ZQ calibration of the selected NVM device channel. 6. The apparatus of claim 1 , wherein the EN hub controller further comprises error correction code (ECC) logic configured to attach an ECC to data being stored in a selected NVM device; determine an error syndrome of data read from the selected NVM device; and correct the data read from the selected NVM device based, at least in part on, the error syndrome. 7. The apparatus of claim 1 , wherein the command logic is further configured to command a selected NVM device to enter a low power standby state if the selected NVM device is idle. 8. A method comprising: initializing, by command logic, a first extensible non-volatile memory (NVM) hub (EN hub) in response to an initialize chain command from an NVM controller, the initializing comprising enumerating each NVM device coupled to the first EN hub and each of one or more associated NVM dies; and performing, by ZQ calibration logic, ZQ calibration of a selected NVM device channel coupling a selected NVM device port and a selected NVM device, the command logic configured to allow memory access operations to continue for one or more unselected NVM devices during ZQ calibration of the selected NVM device channel. 9. The method of claim 8 , wherein the initializing comprises: storing, by the command logic, a first EN hub identifier to the first EN hub; identifying, by the command logic, each NVM device coupled to the first EN hub at a respective NVM device port; assigning, by the command logic, for each NVM device, a volume address to each associated NVM die and associating, by the command logic, each assigned volume address with the respective NVM device port; and providing, by the command logic, a NVM device port identifier and associated one or more volume addresses to the NVM controller. 10. The method of claim 8 , further comprising transmitting, by the command logic, a received command out a downstream port if the received command is not destined for the first EN hub. 11. The method of claim 10 , further comprising regenerating, by the command logic, the received command based, at least in part, on an output from a NVM timing generator. 12. The method of claim 8 , further comprising implementing, by error correction code (ECC) logic, error correction, the implementing comprising: attaching, by the ECC logic, an ECC to data being stored in a selected NVM device; determining, by the ECC logic, an error syndrome of data read from the selected NVM device; and correcting, by the ECC logic, the data read from the selected NVM device based, at least in part on, the error syndrome. 13. The method of claim 8 , further comprising commanding, by the command logic, a selected NVM device to enter a low power standby state if the selected NVM device is idle. 14. The method of claim 8 , further comprising configuring, by EN hub logic, the NVM controller to increase an acceptable communication response time based, at least in part, on a number of EN hubs included in a chain of EN hubs. 15. An system comprising: a processor; a chipset configured to couple the processor to a peripheral device; and a solid state drive (SSD) coupled to the chipset, the SSD comprising: a non-volatile memory (NVM) controller; at least one NVM device; and a first extensible NVM hub (EN hub) comprising: an upstream interface port coupled to a first controller channel port of the NVM controller; a downstream interface port configured to couple the first EN hub to another EN hub or to an NVM device; at least one NVM device port, each NVM device port coupled to a respective NVM device via a respective NVM channel; and an EN hub controller comprising command logic configured to initialize the first EN hub in response to an initialize chain command from the NVM controller, the initialize comprising to enumerate each NVM device coupled to the first EN hub and each of one or more associated NVM dies, the NVM controller configured to receive a memory access request from the processor and to provide a related command to the first EN hub; wherein the EN hub controller further comprises error correction code (ECC) logic configured to attach an ECC to data being stored in a selected NVM device; determine an error syndrome of data read from the selected NVM device; and correct the data read from the selected NVM device based, at least in part on, the error syndrome. 16. The system of claim 15 , further comprising one or more additional EN hubs coupled in a chain to the first EN hub. 17. The system of claim 15 wherein the command logic is configured to store a first EN hub identifier to the first EN hub; identify each NVM device coupled to the first EN hub at a respective NVM device port; assign for each NVM device, a volume address to each associated NVM die and associate each assigned volume address with the respective NVM device port; and provide a NVM device port identifier and associated one or more volume addresses to the NVM controller. 18. The system of claim 15 , wherein the command logic is further configured to transmit a received command out the downstream interface port if the received command is not destined for the first EN hub. 19. The system of claim 18 , wherein the EN hub controller furth

Assignees

Inventors

Classifications

  • in individual solid state devices (G06F11/1004 takes precedence) · CPC title

  • in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

  • Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

  • Non-volatile semiconductor memory arrays · CPC title

  • G06F3/061Primary

    Improving I/O performance · CPC title

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What does patent US9396065B2 cover?
The present disclosure relates to an extensible memory hub. An apparatus may include a first extensible non-volatile memory (NVM) hub (EN hub). The first EN hub includes an upstream interface port configured to couple the first EN hub to an NVM controller or to a second EN hub; a downstream interface port configured to couple the first EN hub to a third EN hub or to a NVM device; at least one N…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification G06F11/1008. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jul 19 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).