Test structures and method for electrical measurement of FinFET fin height

Patent metadata

Field	Value
Publication number	US-10529631-B1
Application number	US-201615269854-A
Country	US
Kind code	B1
Filing date	Sep 19, 2016
Priority date	Sep 17, 2015
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

Methods of measuring fin height electrically for devices fabricated using FinFET technology are disclosed here. One method uses an interleaving comb-like test structure with no gate. The other method extracts fin height from total gate capacitance from FinFETS with varying gate lengths. When a comb-like structure with no gate is used to measure fin height, if there is another structure with a gate is used, then the gate capacitance may be measured to independently measure thickness of gate dielectric.

First claim

The invention claimed is:

1. A method for monitoring height of a fin in a FinFET device by capacitive measurement, the method comprising:
providing a structure comprising a first comb-like arrangement of a plurality of fins with no gates, and a second comb-like arrangement of a plurality of fins with no gates, wherein the first comb-like arrangement and the second comb-like arrangement are interleaved such that an individual fin of the first comb-like arrangement is adjacent to an individual fin of the second comb-like arrangement, wherein the individual fins of the first comb-like structure and the second comb-like structure are substantially of the same height;
measuring a capacitance between the two comb-like arrangements; and
using the measured capacitance to control height of the fin in the FinFET device, wherein the FinFET device uses a technology that merges a source and a drain.

2. The method of claim 1 , wherein the method further comprises:
extracting the height of an individual fin from the measured capacitance using a known value of a dielectric constant of a dielectric between the fins.

3. The method of claim 1 , wherein the method further comprises using the measured capacitance to control the fin height of the FinFET device during manufacture.

4. The method of claim 1 , wherein an epitaxial growth is blocked for the structure as there is no gate, obviating the need for epitaxial growth for contact formation.

5. The method of claim 1 , wherein the method further comprises using a second FinFET device comprising a structure having a gate, wherein gate capacitance measured from the gate of the second FinFET device is independent of the measured capacitance used for monitoring fin height, and wherein gate capacitance measured from the second FinFET device is used to determine a value of a thickness of a gate dielectric layer in the first and second FinFET devices.

6. A method for monitoring fin height in a FinFET device by capacitive measurement, the method comprising:
providing a structure comprising a plurality of FinFET devices having varying lengths of gates but having same fin height throughout the structure;
measuring gate capacitance for each FinFET device;

plotting gate capacitance versus gate length to calculate a slope value that is proportional to the fin height; and
using the measured slope to control the fin height in the FinFET devices.

7. The method of claim 6 , wherein gate capacitance is measured at inversion.

8. The method of claim 6 , wherein the fin height is extracted from the slope according to the following equation:

Slope
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T
inv

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i
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)

.

9. The method of claim 8 , wherein value of T inv is dictated by Design Rule Manual (DRM).

10. The method of claim 6 , wherein the slope is calculated-using the FinFET devices whose gate lengths are shorter than a threshold value.

11. The method of claim 6 , further comprising varying a bias applied to gates of the FinFET devices based on the length of the gate.

12. The method of claim 11 , wherein the bias applied is different for nMOS devices compared to pMOS devices having the same gate length.

13. A method of determining fin height for a fin field-effect transistor device (FinFET) based on capacitance measurement, the method performable during manufacturing without making process modifications, the method comprising:
in a first FinFET disposed on a semiconductor substrate, the first FinFET comprising a plurality of fins forming transistor source and drain regions, wherein a transistor gate and gate contact are excluded from the first FinFET, wherein the first FinFET comprises a structure having a first comb-like configuration of parallel fins interleaved with a second comb-like configuration of parallel fins, wherein each individual fin of the first comb-like configuration of parallel fins is disposed on the semiconductor substrate adjacent to at least one individual fin of the second comb-like configuration of parallel fins, and wherein individual fins of the first and second comb-like structures are substantially of the same fin height:
measuring a fin-to-fin capacitance between adjacent fins of the plurality of fins in the first and second comb-like structures; and
using the measured fin-to-fin capacitance to determine fin height for the first FinFET.

14. The method of claim 13 further comprising:
in a test structure comprising a second FinFET comprising a transistor gate and gate contact and a plurality of parallel fins forming transistor source drain regions of the second FinFET:
measuring a gate capacitance of the second FinFET, wherein the gate capacitance of the second FinFET is measured independently from measuring the fin-to-fin capacitance of the first FinFET; and
determining a gate dielectric layer thickness for the transistor gate of the second FinFET based on the measured gate capacitance.

15. A method for determining fin height in a fin field-effect transistor device (FinFET) based on capacitance measurement, the method performable during manufacturing without making process modifications, the method comprising:
in a structure disposed on a semiconductor substrate embracing (1) a first FinFET comprising a plurality of fins forming transistor source drain regions and a transistor gate of a first gate length and (2) a second FinFET comprising a plurality of fins forming transistor source drain regions and a transistor gate of a second gate length different from the first gate length, wherein fin height for the plurality of fins in the first and second FinFETs is substantially the same throughout the structure:
measuring gate capacitance of the first FinFET and gate capacitance of the second FinFET;
calculating the slope of gate capacitance versus gate length for the first gate length and measured gate capacitance of the first FinFET and for the second gate length and measured gate capacitance of the second FinFET; and
determining fin height for the first FinFET and the second FinFET based on the calculated slope.

16. The method of claim 15 wherein the fin height is determined from the slope according to the following equation:

Slope
≈

ɛ
ox

Assignees

• Pdf Solutions Inc

Inventors

• Saxena Sharad
• Cheng Jianjun
• Yu Yuan

Classifications

• H10P74/23 Primary

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H01L29/66795

  Electricity · mapped topic

• H01L22/20 Primary

  Electricity · mapped topic

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P74/277 Primary

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title