Methods of manufacturing a semiconductor device

Patent metadata

Field	Value
Publication number	US-10529618-B2
Application number	US-201815870175-A
Country	US
Kind code	B2
Filing date	Jan 12, 2018
Priority date	Jun 8, 2017
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

A method of manufacturing a semiconductor device is disclosed. The method includes forming a first insulting layer on a substrate, forming a first conductor pattern in the first insulating layer, forming a second insulating layer on the first insulating layer, and forming a second wiring pattern and a contact via in the second insulating layer, wherein a top surface of the first insulating layer is higher than a top surface of the first conductor pattern.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a first insulating interlayer on a substrate, the first insulating interlayer containing lower wirings of which upper surfaces are exposed;
selectively forming a second insulating interlayer on an exposed upper surface of the first insulating interlayer;
sequentially forming a first etch stop layer and a third insulating interlayer on the lower wirings and the second insulating interlayer;
forming a trench and first and second via holes, the trench extending through an upper portion of the third insulating interlayer, the first via hole extending through a lower portion of the third insulating interlayer and a portion of the first etch stop layer to be connected to the trench, the second via hole extending through the second insulating interlayer to expose a first wiring of the lower wirings and to be connected to the first via hole, and the second via hole having a width smaller than that of the first via hole; and
forming an upper wiring and a via, the upper wiring filling the trench, and the via filling the first and second via holes,
wherein forming the trench and the first and second via holes includes:
sequentially forming first and second masks on the third insulating interlayer;
etching an upper portion of the third insulating interlayer using the first and second masks as an etching mask to form a preliminary via hole overlapping the first wiring and a portion of the second insulating interlayer adjacent to the first wiring;
after removing the second mask, etching the third insulating interlayer using the first mask as an etching mask to expose a portion of the first etch stop layer on the first wiring and on the portion of the second insulating interlayer adjacent to the first wiring; and
removing the exposed portion of the first etch stop layer to expose an upper surface of the first wiring and the portion of the second insulating interlayer adjacent to the first wiring.

2. The method of claim 1 , selectively forming the second insulating interlayer on the exposed upper surface of the first insulating interlayer includes performing an atomic layer deposition (ALD) process such that the second insulating interlayer is selectively grown on the exposed upper surface of the first insulating interlayer, the ALD process including:
i) providing a silicon-containing precursor;
ii) providing a first purge gas after providing the silicon-containing precursor;
iii) providing an oxidizer after providing the first purge gas;
iv) providing a second purge gas after providing the oxidizer;
v) providing a reducer after providing the second purge gas; and
vi) providing a third purge gas after providing the reducer.

3. The method of claim 2 , wherein steps i) to iv) are repeatedly performed.

4. The method of claim 1 , wherein the first to third insulating interlayers include a low-k dielectric material, and the first etch stop layer includes silicon carbonitride or silicon nitride.

5. The method of claim 1 , wherein forming the trench and the first and second via holes includes:
sequentially forming a second etch stop layer and the first and second masks on the third insulating interlayer;
etching the second etch stop layer and an upper portion of the third insulating interlayer using the first and second masks as an etching mask to form a preliminary via hole overlapping the first wiring and a portion of the second insulating interlayer adjacent to the first wiring;
forming a sacrificial layer on the exposed upper surface of the first wiring and the exposed portion of the second insulating interlayer;
etching the second etch stop layer and the third insulating interlayer using the sacrificial layer and the first mask as an etching mask to expose a portion of the first etch stop layer; and
removing the sacrificial layer.

6. The method of claim 1 , wherein the second via hole is formed at the same level as that of the second insulating interlayer, and the width of the second via hole is equal to that of the first wiring.

7. The method of claim 1 , wherein the selectively forming of the second insulating interlayer on the exposed upper surface of the first insulating interlayer comprises forming the second insulating interlayer on the first insulating interlayer while without forming a layer on the lower wirings of which surfaces are exposed.

8. The method of claim 1 , wherein the second via hole exposes a portion of an upper surface of the first wiring.

9. The method of claim 1 , wherein selectively forming the second insulating interlayer on the exposed upper surface of the first insulating interlayer includes forming the second insulating interlayer on an upper surface of a portion of the first insulating interlayer adjacent to the first wiring of the lower wirings, and wherein the second insulating interlayer is not formed on upper surfaces of portions of the first insulating interlayer adjacent to other lower wirings.

10. A method of manufacturing a semiconductor device, the method comprising:
forming a first insulating interlayer on a substrate, the first insulating interlayer containing lower wirings of which upper surfaces of the lower wirings are exposed and at a height lower than upper surfaces of the first insulating interlayer;
sequentially forming a first etch stop layer and a second insulating interlayer on the lower wirings and the first insulating interlayer;
forming a trench and first and second via holes, the trench extending through an upper portion of the second insulating interlayer, the first via hole extending through a lower portion of the second insulating interlayer and a portion of the first etch stop layer to be connected to the trench, and the second via hole extending through an upper portion of the first insulating interlayer to expose a first wiring of the lower wirings and to be connected to the first via hole; and
forming an upper wiring and a via, the upper wiring filling the trench, and the via filling the first and second via holes,
wherein forming the trench and the first and second via holes includes:
sequentially forming first and second masks on the second insulating interlayer;
etching an upper portion of the second insulating interlayer using the first and second masks as an etching mask to form a preliminary via hole overlapping the first wiring and a portion of the first insulating interlayer adjacent to the first wiring;
after removing the second mask, etching the second insulating interlayer using the first mask as an etching mask to expose a portion of the first etch stop layer on the first wiring and on the portion of the first insulating interlayer adjacent to the first wiring; and
removing the exposed portion of the first etch stop layer to expose an upper surface of the first wiring and the portion of the first insulating interlayer adjacent to the first wiring.

11. The method of claim 10 , wherein forming the trench and the first and second via holes includes:
sequentially forming a second etch stop layer and first and second masks on the second insulating interlayer;
etching the second etch stop layer and an upper portion of the second insulating interlayer using the first and second masks as an etching mask to form a preliminary via hole overlapping the first wiring and a portion of the first insulating interlayer adjacent to the first wiring;
forming a sacrificial layer on the exposed upper surface of the first wiring and on the exposed portion of the first insulating interlayer;
etching the second etch stop layer and the second insulating interlayer using the sacrificial layer and the first mask as an etching

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lu Siqing
• Ahn Sang-Hoon
• Chen Xinglong
• Kim Ki-Hyun
• Shim Kyu-In

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P14/61

  using masks · CPC title

• H10P76/2041

  Photolithographic processes · CPC title

• H10P50/283

  by chemical means · CPC title