Memory channel driver with echo cancellation

Patent metadata

Field	Value
Publication number	US-10528515-B2
Application number	US-201715634991-A
Country	US
Kind code	B2
Filing date	Jun 27, 2017
Priority date	Jun 27, 2017
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

An apparatus is described that includes a memory channel driver circuit having first driver circuitry to drive a data signal on a memory channel and second driver circuitry to drive an echo cancellation signal on the memory channel. The echo cancellation signal includes echo cancellation pulses that follow corresponding pulses of the data signal by an amount of time that causes the echo cancellation pulses to reduce reflections of the corresponding pulses of the data signal at a memory device that is coupled to the memory channel.

First claim

The invention claimed is:

1. An apparatus, comprising:
a memory channel driver circuit comprising first driver circuitry to drive a data signal on a memory channel data wire and second driver circuitry to drive an echo cancellation signal on said memory channel data wire, said echo cancellation signal comprising echo cancellation pulses that follow corresponding pulses of said data signal on said memory channel data wire by an amount of time that causes said echo cancellation pulses to reduce reflections of said corresponding pulses of said data signal on said memory channel data wire at a memory device that is coupled to said memory channel data wire, the second driver circuitry to also generate echo cancellation training pulses in which delay is varied across a first set of the echo cancellation training pulses and amplitude is varied across a second, different set of the echo cancellation training pulses.

2. The apparatus of claim 1 wherein said memory device is a DIMM card.

3. The apparatus of claim 2 wherein said DIMM card is closest to said memory channel driver circuit on said memory channel data wire.

4. The apparatus or claim 1 wherein said memory channel driver circuit is integrated on a memory controller.

5. The apparatus of claim 1 wherein said memory channel driver circuit further comprises a delay circuit coupled to said second driver circuit, said delay circuit to receive said data signal, said delay circuit to delay said data signal by said amount of time.

6. The apparatus of claim 1 wherein said first and second driver circuits are comprised of respective parallel legs of P type and N type transistors.

7. The apparatus of claim 6 further comprising additional parallel legs of transistors to impart pre-emphasis on said data signal.

8. The apparatus of claim 1 further comprising training circuitry to determine an appropriate amplitude for said echo cancellation pulses and to determine said amount of time.

9. A computing system, comprising:
one or more processing cores;
a main memory;
a memory controller coupled to said main memory with a memory channel, said memory controller comprising a memory channel driver circuit, said memory channel driver circuit comprising first driver circuitry to drive a data signal on a data wire of said memory channel and second driver circuitry to drive an echo cancellation signal on said data wire, said echo cancellation signal comprising echo cancellation pulses that follow corresponding pulses of said data signal on said data wire by an amount of time that causes said echo cancellation pulses to reduce reflections of said corresponding pulses of said data signal on said data wire at a memory device that is coupled to said memory channel, the second driver circuitry to also generate echo cancellation training pulses in which delay is varied across a first set of the echo cancellation training pulses and amplitude is varied across a second, different set of the echo cancellation training pulses.

10. The computing system of claim 9 wherein said memory device is a DIMM card.

11. The computing system of claim 10 wherein said DIMM card is closest to said memory channel driver circuit on said memory channel.

12. The computing system or claim 9 wherein said memory channel driver circuit is integrated on a memory controller.

13. The computing system of claim 9 wherein said memory channel driver circuit further comprises a delay circuit coupled to said second driver circuit, said delay circuit to receive said data signal, said delay circuit to delay said data signal by said amount of time.

14. The computing system of claim 9 wherein said first and second driver circuits are comprised of respective parallel legs of P type and N type transistors.

15. The computing system of claim 14 further comprising additional parallel legs of transistors to impart pre-emphasis on said data signal.

16. A method, comprising:
training a memory controller driver circuit by:
varying delay across a first set of echo cancellation pulses;
varying amplitude across a second, different set of echo cancellation pulses; and,
determining a combination of echo cancellation pulse amplitude and delay that reduces reflections at a memory device that is coupled to a memory channel that is driven by said memory controller driver circuit.

17. The method of claim 16 wherein said memory device is a DIMM card.

18. The method of claim 17 wherein said DIMM card is closest to said memory controller driver circuit as compared to any other DIMM cards that are coupled to said memory channel.

19. The method of claim 16 wherein said method further comprising performing pre-emphasis training for data pulses that are driven by said memory controller driver circuit.

Assignees

• Intel Corp

Inventors

• Li Qin
• Lin Changhong
• Mccall James A
• Muljono Harry

Classifications

• H04B3/23

  using a replica of transmitted signal in the time domain, e.g. echo cancellers · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G06F13/1689

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G11C5/063 Primary

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G06F13/4072 Primary

  Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002) · CPC title