Power management system for a bus interface system

Patent metadata

Field	Value
Publication number	US-10528502-B2
Application number	US-201514659371-A
Country	US
Kind code	B2
Filing date	Mar 16, 2015
Priority date	Dec 18, 2013
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

Embodiments of bus interface systems are disclosed. In one embodiment, a bus interface system includes a master bus controller and a slave bus controller coupled along a bus line. The master bus controller is configured to generate an input data signal that is received by the slave bus controller along the bus line. The slave bus controller includes power conversion circuitry configured to convert the input data signal from the master bus controller into a supply voltage. By providing the power conversion circuitry, the slave bus controller is powered using the input data signal and without requiring an additional bus line to transfer a supply voltage to the slave bus controller.

First claim

What is claimed is:

1. A bus interface system, comprising:
a single bus line consisting of a single wire;
a master bus controller coupled to the single bus line, the master bus controller is configured to generate a first input data signal and to transmit the first input data signal along the single bus line; and
a slave bus controller coupled to the single bus line, wherein no other bus line connects the master bus controller and the slave bus controller, and wherein the slave bus controller is configured to receive the first input data signal from the master bus controller over the single bus line, wherein the slave bus controller comprises power conversion circuitry configured to convert the first input data signal into a first supply voltage.

2. The bus interface system of claim 1 wherein the power conversion circuitry comprises:
a reservoir capacitor coupled to generate the first supply voltage;
a rectifier coupled between the single bus line and the reservoir capacitor so that the rectifier charges the reservoir capacitor with the first input data signal and so that the rectifier blocks discharge from the reservoir capacitor; and
a first switchable bypass path coupled between the single bus line and the reservoir capacitor such that the first switchable bypass path is coupled to bypass the rectifier, wherein the first switchable bypass path is switchable to be opened and to be closed.

3. The bus interface system of claim 2 , wherein:
the master bus controller is configured to initiate communication of a data frame along the single bus line with the first input data signal; and
the slave bus controller is configured to open the first switchable bypass path in the power conversion circuitry in response to the first input data signal indicating that the master bus controller has initiated the communication of the data frame.

4. The bus interface system of claim 3 , wherein
the master bus controller is configured to hold the first input data signal in a charging state during a communication interlude between the master bus controller and the slave bus controller; and
the slave bus controller is configured to close the first switchable bypass path in the power conversion circuitry in response to the communication interlude.

5. The bus interface system of claim 2 wherein:
the first switchable bypass path includes a first resistor connected in series within the first switchable bypass path.

6. The bus interface system of claim 5 wherein the power conversion circuitry further comprises a second switchable bypass path that is switchable to be opened and to be closed and wherein the second switchable bypass path is connected to the first switchable bypass path such that the second switchable bypass path is coupled to bypass the first resistor in the first switchable bypass path.

7. The bus interface system of claim 6 wherein:
the master bus controller is configured to initiate communication of a data frame along the single bus line with the first input data signal; and
the master bus controller is configured to hold the first input data signal in a charging state during a communication interlude between the master bus controller and the slave bus controller; and
the slave bus controller is configured to:
open the first switchable bypass path in the power conversion circuitry in response to the first input data signal indicating that the master bus controller has initiated the communication of the data frame;
close the first switchable bypass path in the power conversion circuitry in response to the communication interlude;
close the second switchable bypass path in the power conversion circuitry in response to the communication interlude; and
open the second switchable bypass path once a charging time interval has passed after closing the second switchable bypass path in the power conversion circuitry in response to the communication interlude.

8. The bus interface system of claim 6 further comprising a decoupling stage coupled between the single bus line and the rectifier.

9. The bus interface system of claim 8 wherein the master bus controller comprises a voltage regulation circuit and a data modulator, wherein:
the data modulator is configured to generate the first input data signal; and
the voltage regulation circuit is configured to convert a power source voltage into a second supply voltage that powers the data modulator.

10. The bus interface system of claim 2 wherein:
the first switchable bypass path only includes a first switch coupled in series within the first switchable bypass path, the first switch is switchable so as to open and close the first switchable bypass path.

11. The bus interface system of claim 10 wherein the power conversion circuitry further comprises a second switchable bypass path coupled between the single bus line and the reservoir capacitor such that the second switchable bypass path is coupled to bypass the rectifier, wherein the second switchable bypass path comprises:
a second switch coupled in series within the second switchable bypass path so as to open and close the second switchable bypass path; and
a first resistor coupled in series within the second switchable bypass path.

12. The bus interface system of claim 2 wherein the power conversion circuitry further comprises a decoupling stage coupled between the single bus line and the rectifier.

13. The bus interface system of claim 12 wherein the decoupling stage comprises a resistor connected in series between the single bus line and the rectifier.

14. The bus interface system of claim 13 wherein the power conversion circuitry further comprises a second switchable bypass path that is switchable to be opened and to be closed, the second switchable bypass path is coupled between the single bus line and the rectifier so as to bypass the resistor.

15. The bus interface system of claim 14 wherein:
the master bus controller is configured to initiate communication of a data frame along the single bus line with the first input data signal;
the master bus controller is configured to hold the first input data signal in a charging state during a communication interlude between the master bus controller and the slave bus controller; and
the slave bus controller is configured to:
close the second switchable bypass path in the power conversion circuitry in response to the communication interlude; and
open the second switchable bypass path once a charging time interval has passed after closing the second switchable bypass path in the power conversion circuitry in response to the communication interlude.

16. The bus interface system of claim 2 wherein the master bus controller comprises a voltage regulation circuit and a data modulator, wherein:
the data modulator is configured to generate the first input data signal so that the first input data signal defines a set of data pulses during a data frame;
the voltage regulation circuit is configured to convert a power source voltage into a second supply voltage that powers the data modulator; and
a second switchable bypass path is connected between the voltage regulation circuit and the single bus line so as to bypass the data modulator, wherein the second switchable bypass path is switchable to be opened and to be closed.

17. The bus interface system of claim 16 wherein the slave bus controller is configured to close the second switchable bypass path in the power conversion circuitry in response to a communication interlude.

18. The bus interface system of claim 2 wherein the first

Assignees

• Rf Micro Devices Inc
• Qorvo Us Inc

Inventors

• Ngo Christopher Truong
• Hietala Alexander Wayne
• Iversen Christian Rye
• Bauder Ruediger

Classifications

• G06F13/4072

  Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002) · CPC title

• G06F13/364 Primary

  using independent requests or grants, e.g. using separated request and grant lines · CPC title

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F1/10 Primary

  Distribution of clock signals {, e.g. skew} · CPC title