Serial bus buffer with noise reduction

Patent metadata

Field	Value
Publication number	US-9519612-B2
Application number	US-201414160900-A
Country	US
Kind code	B2
Filing date	Jan 22, 2014
Priority date	Apr 4, 2013
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

Disclosed is a digital communication control system having a serial bus buffer that includes a primary interface adapted to support serial communication over a primary bus, a buffered interface adapted to support serial communication over a buffered bus, and a controller coupled between the primary bus and the buffered bus. The primary bus is coupled to a first device and at least one second device and the buffered bus is coupled to at least one third device. The controller is adapted to receive a first data signal and a clock signal at the primary interface and replicate the first data signal and the clock signal at the buffered interface.

First claim

What is claimed is:

1. A serial bus buffer comprising:
a primary interface coupled to a primary serial data line and a primary serial clock line of a primary bus, wherein the primary bus is coupled to a first device and at least one second device;
a buffered interface coupled to a buffered serial data line and a buffered serial clock line of a buffered bus, wherein the buffered bus is coupled to at least one third device; and
a controller coupled between the primary interface and the buffered interface and configured to:
receive a first data signal and a clock signal at the primary interface; and
replicate the first data signal and the clock signal at the buffered interface upon receiving a first command within the first data signal to execute a first mode that passes the first data signal and the clock signal from the primary interface to the buffered interface.

2. The serial bus buffer of claim 1 wherein the first device is a master device and the at least one third device is a sensitive slave device.

3. The serial bus buffer of claim 2 wherein the at least one second device is a non-sensitive slave device.

4. The serial bus buffer of claim 1 wherein the buffered bus comprises at least one filter and wherein the at least one filter reduces spurious signals coupled to the buffered bus.

5. The serial bus buffer of claim 4 wherein the at least one filter is a low corner frequency low pass filter.

6. The serial bus buffer of claim 1 wherein the controller is further configured to provide a high impedance output at the buffered interface such that the first data signal and the clock signal are not replicated at the buffered interface.

7. A serial bus buffer comprising:
a primary interface coupled to a primary serial data line and a primary serial clock line of a primary bus, wherein the primary bus is coupled to a first device and at least one second device;
a buffered interface coupled to a buffered serial data line and a buffered serial clock line of a buffered bus, wherein the buffered bus is coupled to at least one third device; and
a controller coupled between the primary interface and the buffered interface and configured to:
receive a first data signal and a clock signal at the primary interface;
select a first drive level from one of a first plurality of available drive levels; and
replicate the first data signal and the clock signal at the first drive level at the buffered interface upon receiving a first command within the first data signal to execute a first mode that passes the first data signal and the clock signal from the primary interface to the buffered interface.

8. The serial bus buffer of claim 7 wherein the controller is further configured to:
receive a second data signal at the buffered interface; and
replicate the second data signal at the primary interface.

9. The serial bus buffer of claim 8 wherein the controller is further configured to:
select a second drive level from a second plurality of available drive levels; and
replicate the second data signal at the second drive level at the primary interface.

10. The serial bus buffer of claim 7 wherein the controller is further configured to:
during a first mode, replicate the first data signal and the clock signal at the buffered interface; and
during a second mode, the first data signal and the clock signal are not replicated at the buffered interface.

11. The serial bus buffer of claim 10 wherein during the second mode, the controller is further configured to provide a high impedance output at the buffered interface such that the first data signal and the clock signal are not replicated at the buffered interface.

12. A serial bus buffer comprising:
a primary interface coupled to a primary serial data line and a primary serial clock line of a primary bus, wherein the primary bus is coupled to a first device and at least one second device;
a buffered interface coupled to a buffered serial data line and a buffered serial clock line of a buffered bus, wherein the buffered bus is coupled to at least one third device; and
a controller coupled between the primary interface and the buffered interface and configured to:
receive a first data signal and a clock signal at the primary interface;
replicate the first data signal and the clock signal at the buffered interface upon receiving a first command within the first data signal to execute a first mode that passes the first data signal and the clock signal from the primary interface to the buffered interface;
receive a second data signal at the buffered interface; and
replicate the second data signal at the primary interface upon receiving a second command within the second data signal to execute a second mode that passes the second data signal and the clock signal from the buffer interface to the primary interface.

13. The serial bus buffer of claim 12 wherein the controller is further configured to:
select a first drive level from a first plurality of available drive levels; and
replicate the first data signal and the clock signal at the first drive level at the buffered interface.

14. The serial bus buffer of claim 13 wherein the controller is further configured to:
select a second drive level from a second plurality of available drive levels; and
replicate the second data signal at the second drive level at the primary interface.

15. The serial bus buffer of claim 12 wherein the controller is further configured to:
during a first mode:
replicate the first data signal and the clock signal at the buffered interface;
receive the second data signal at the buffered interface; and
replicate the second data signal at the primary interface; and

during a second mode:
the first data signal and the clock signal are not replicated at the buffered interface;
the second data signal is not received at the buffered interface; and
the second data signal is not replicated at the primary interface.

16. The serial bus buffer of claim 15 wherein during the second mode, the controller is further configured to provide a high impedance output at the buffered interface such that:
the first data signal and the clock signal are not replicated at the buffered interface;
the second data signal is not received at the buffered interface; and
the second data signal is not replicated at the primary interface.

17. A serial bus buffer comprising:
a primary interface coupled to a primary serial data line and a primary serial clock line of a primary bus, wherein the primary bus is coupled to a first device and at least one second device;
a buffered interface coupled to a buffered serial data line and a buffered serial clock line of a buffered bus, wherein the buffered bus is coupled to at least one third device; and
a controller coupled between the primary interface and the buffered interface and to:
receive a first data signal and a clock signal at the primary interface;
during a first mode, replicate the first data signal and the clock signal at the buffered interface upon receiving a first command within the first data signal to execute the first mode that passes the first data signal and the clock signal from the primary interface to the buffered interface; and
during a second mode, the first data signal and the clock signal are not replicated at the buffered interface upon receiving a second command within the first data signal to execute the second mode that blocks the passing of the first data signal and the clock signal from the primary interface to the buffered interface.

18. The ser

Assignees

• Rf Micro Devices Inc
• Qorvo Us Inc

Inventors

• Hietala Alexander Wayne
• Ngo Christopher Truong
• Bolton Eric K

Classifications

• G06F13/4291 Primary

  using a clocked protocol · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title