Storage devices including logical to physical address mapping and methods of operating

Patent metadata

Field	Value
Publication number	US-10528466-B2
Application number	US-201816002151-A
Country	US
Kind code	B2
Filing date	Jun 7, 2018
Priority date	Jun 9, 2017
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

A method of operating a storage device including a nonvolatile memory can be provided by receiving, from a host, address change information including changing logical addresses for data to be stored in the nonvolatile memory. Physical addresses can be sequentially allocated to the changing logical addresses included in the address change information to provide a first journal. A portion of at least one physical address allocated to the changing logical addresses can be removed to provide a second journal and the second journal can be stored in the nonvolatile memory.

First claim

What is claimed is:

1. A method of operating a storage device including a nonvolatile memory having a plurality of blocks, each of the plurality of blocks including a plurality of pages with a respective physical address for each page, the method comprising:
receiving at least one address unit including a plurality of logical addresses;
sorting the plurality of logical addresses in ascending or descending order to provide a plurality of sorted logical addresses; and
sequentially allocating a physical address of a first level page in each block to the plurality of sorted logical addresses in a first mapping table until all first level pages are allocated; and then
sequentially allocating a physical address of a second level page in each block to the plurality of sorted logical addresses in the first mapping table.

2. The method of claim 1 , wherein the plurality of blocks are addressed using channel information and way information in the first mapping table, the channel information is configured to select a group of the blocks included in the plurality of blocks and the way information is configured to select one block included in the group of the blocks, the method further comprises:
removing the channel information and way information from the first mapping table to provide a second mapping table.

3. The method of claim 2 , wherein the nonvolatile memory comprises super blocks including at least one of the plurality of blocks, and the physical addresses include super block information about a super block including a corresponding page and page number information about a corresponding page number.

4. The method of claim 2 , further comprising:
receiving an access request to at least one logical address among the plurality of logical addresses; and
adding the channel information and the way information to a physical address allocated to the at least one logical address in the second mapping table.

5. The method of claim 2 , further comprising:
storing the second mapping table in the nonvolatile memory.

6. The method of claim 1 , further comprising:
storing the first mapping table in at least one buffer.

7. The method of claim 1 , wherein receiving the at least one address unit including a plurality of logical addresses comprises receiving plurality of address units,
wherein sequentially allocating the physical address of the first level page in each block to the plurality of sorted logical addresses further comprises:
sequentially allocating the physical address of the first level page in each block to the plurality of sorted logical addresses to include identification information for the plurality of address units.

8. The method of claim 1 , further comprising:
receiving address change information for the plurality of logical addresses;
generating a first journal by sequentially allocating physical addresses to changing logical addresses included in the address change information;
generating a second journal by allocating physical addresses to changing logical addresses; and
storing the second journal in the nonvolatile memory.

9. The method of claim 8 , wherein generating the second journal comprises:
allocating a first physical address including changing logical address number information to a first changing logical address among the changing logical addresses; and
skipping allocating of the physical addresses to remaining changing logical addresses except for a first changing logical address.

10. A method of operating a storage device including a nonvolatile memory, the method comprising:
receiving, from a host, address change information including changing logical addresses for data to be stored in the nonvolatile memory;
sequentially allocating physical addresses to the changing logical addresses included in the address change information to provide a first journal;
removing a portion of at least one physical address allocated to the changing logical addresses to provide a second journal; and
storing the second journal in the nonvolatile memory.

11. The method of claim 10 , wherein the nonvolatile memory includes a plurality of blocks, each of the plurality of blocks including a plurality of pages;
wherein sequentially allocating physical addresses to the changing logical addresses comprises:
sequentially allocating a physical address of a first level page in each block to the changing logical addresses until all first level pages are allocated; and then
sequentially allocating a physical address of a second level page in each block to the changing logical addresses.

12. The method of claim 10 , wherein removing the portion of at least one physical address allocated to the changing logical addresses to provide a second journal comprises:
allocating a first physical address including changing logical address number information indicating a number of the changing logical addresses to a first one of the changing logical addresses.

13. The method of claim 12 , further comprising:
reading the second journal from the nonvolatile memory;
restoring the portion of the at least one physical address to provide a restored first journal
storing the restored first journal in a buffer of the storage device.

14. The method of claim 10 , wherein the storage device further comprises a buffer, and
the method further comprises:
storing the first journal in the buffer;
receiving an access request to at least one of the changing logical addresses; and
outputting at least one physical address allocated to the at least one of the changing logical addresses based on the first journal, in response to the access request.

15. A storage device comprising:
a nonvolatile memory comprising a plurality of pages corresponding to a plurality of physical addresses, respectively, the nonvolatile memory divided into a meta area storing addresses, and a user area storing data;
a flash translation layer (FTL) configured to receive a plurality of logical addresses from an external source and configured to allocate the plurality of physical addresses to the plurality of logical addresses; and
an address sorter configured to sort the plurality of logical addresses in ascending or descending order to provide a plurality of sorted logical addresses and configured to output the plurality of sorted logical addresses to the flash translation layer,
wherein the flash translation layer is configured to deterministically allocate the plurality of physical addresses to the sorted plurality of logical addresses.

16. The storage device of claim 15 , wherein the plurality of logical addresses comprise N logical addresses, wherein N is a natural number greater than 1,
the storage device further comprises a buffer storing the N logical addresses, and
the address sorter repeatedly reads at least one of the N logical addresses from the buffer to provide read logical addresses and sorts the read logical addresses until all of the N logical addresses are sorted.

17. The storage device of claim 16 , wherein the buffer stores a mapping table including mapping information of the logical addresses and the physical addresses.

18. The storage device of claim 16 , wherein the plurality of pages comprise a plurality of blocks,
the plurality of blocks are divided according to channels and ways, each channel connected to at least one of the plurality of blocks, the ways indicating an order in which the plurality of blocks are connected to the channels, and
the flash translation layer omits channel and way information from the physical addresses.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jong-Won
• Shmuel Dashevsky
• Twitto Moshe
• Erez Elona
• Hof Eran
• Kong Jun-Jin
• Dor Avner
• Erlihson Michael

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F2212/2022

  Flash memory · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F12/06 Primary

  Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (G06F12/08 takes precedence) · CPC title

• G06F2212/1008

  Correctness of operation, e.g. memory ordering · CPC title