Structure design generation for fixing metal tip-to-tip across cell boundary

Patent metadata

Field	Value
Publication number	US-10527932-B2
Application number	US-201916239165-A
Country	US
Kind code	B2
Filing date	Jan 3, 2019
Priority date	Dec 11, 2015
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

An apparatus including a memory storing instructions and a processor executing the instructions to perform a method including: performing error processing of an initial design file layout; detecting a tip-to-tip (T2T) structure design violation at a design cell boundary for a metal layer above (Ma) a via (Vx) at a tip of the Ma for the initial design file layout for a semiconductor structure based on a library of pattern rules; retargeting the Vx for generating a resulting design file layout of the semiconductor structure; and generating a physical semiconductor structure based on the resulting design file layout of the semiconductor structure.

First claim

What is claimed is:

1. An apparatus comprising:
a memory storing instructions; and
a processor executing the instructions to perform a method comprising:
performing, by a processor, error processing of an initial design file layout;
detecting a tip-to-tip (T2T) structure design violation at a design cell boundary for a metal layer above (Ma) a via (Vx) at a tip of the Ma for the initial design file layout for a semiconductor structure based on a library of pattern rules;
retargeting the Vx for generating a resulting design file layout of the semiconductor structure; and
generating a physical semiconductor structure based on the resulting design file layout of the semiconductor structure.

2. The apparatus of claim 1 , wherein the error processing uses the library of pattern rules that comprises design rules for pattern checking and retargeting tables.

3. The apparatus of claim 2 , wherein retargeting the Vx is based on the processor adjusting any of the Ma, a metal layer (Mb) below the Vx that connects the Ma through the Vx and the Vx that connects the Ma and the Mb.

4. The apparatus of claim 3 , wherein the method further comprises:
determining whether the Vx is at a first metal line end (LE);
upon the Vx being at the metal LE, setting a T2T design value for the resulting design file layout for the semiconductor structure;
analyzing the Ma, the Vx and the Mb to determine whether the Mb is at a second metal LE; and
upon the Vx not being at the first metal LE, relaxing T2T requirement values for the initial design file layout for the semiconductor structure.

5. The apparatus of claim 4 , wherein the method further comprises:
upon a determination that the Mb is not at the second metal LE, determining the Mb available space at a common edge (E_VxMb) between the Mb and the Vx; and
upon a determination that the Mb available space at E_VxMb is greater than a minimum allowable space for the Mb, jogging a design value for the Mb, retargeting a design value for the Vx using the retargeting tables and executing a design process or using a first set of predetermined design values, otherwise upon a determination that the Ma available space at a common edge (E_VxMa) between the Ma and the Vx is greater than a minimum allowable space for the Ma, jogging a design value for the Ma, retargeting the design value for the Vx using the retargeting tables and executing the design process or using a second set of predetermined design values.

6. The apparatus of claim 5 , wherein the method further comprises:
upon a determination that the resulting design file layout for the semiconductor structure falls outside of a three sigma area for the Vx, re-determining whether the Mb is at the second metal LE, otherwise outputting the resulting design file layout as a final design file layout for the semiconductor structure.

7. The apparatus of claim 4 , wherein the method further comprises:
upon a determination that the Mb is at the second metal LE, upon a determination that the Ma available space at E_VxMa is greater than the minimum allowable space for the Ma and the Mb available space at E_VxMb is greater than the Mb minimum space, jogging the design value for the Ma and for the Mb, retargeting the design value for the Vx using the retargeting tables and executing the design process or using a third set of predetermined design values, otherwise inserting a dummy track into the initial design file layout for the semiconductor structure, wherein the retargeting of the Vx comprises retargeting, using the retargeting tables, metal below the Vx in a vertical direction to avoid Vx metal shorting.

8. A system comprising:
a memory storing a design application;
a processor executing the design application that is configured to:
perform error processing of an initial design file layout;
detect a tip-to-tip (T2T) structure design violation at a design cell boundary for a metal layer above (Ma) a via (Vx) at a tip of the Ma for the initial design file layout for a semiconductor structure based on a library of pattern rules;
upon detection of the T2T structure design violation, retarget the Vx for generating a resulting design file layout of the semiconductor structure; and
generate a physical semiconductor structure based on the resulting design file layout of the semiconductor structure.

9. The system of claim 8 , wherein the error processing uses the library of pattern rules that comprises design rules for pattern checking and retargeting tables, and retarget of the Vx is based on adjusting any of the Ma, a metal layer (Mb) below the Vx that connects the Ma through the Vx and the Vx that connects the Ma and the Mb.

10. The system of claim 9 , wherein the application is further configured to:
determine, by the computer, whether the Vx is at a first metal line end (LE);
upon the Vx being at the metal LE, set, by the computer, the T2T design value for the design file layout for the semiconductor structure;
analyze, by the computer, the Ma, the Vx and the Mb to determine whether the Mb is at a second metal LE; and
upon the Vx not being at the first metal LE, relax, by the computer, T2T requirement values for the initial design file layout for the semiconductor structure.

11. The system of claim 10 , wherein the design application is further configured to:
upon a determination that the Mb is not at the second metal LE, determine, by the computer, the Mb available space at a common edge (E_VxMb) between the Mb and the Vx; and
upon a determination that the Mb available space at E_VxMb is greater than a minimum allowable space for the Mb, jog, by the computer, a design value for the Mb, retarget a design value using the retargeting tables for the Vx and execute, by the computer, a design process or using a first set of predetermined design values, otherwise upon a determination that the Ma available space at a common edge (E_VxMa) between the Ma and the Vx is greater than a minimum allowable space for the Ma, jog, by the computer, a design value for the Ma, retarget the design value using the retargeting tables for the Vx and execute, by the computer, the design process or using a second set of predetermined design values.

12. The system of claim 10 , wherein the design application is further configured to:
upon a determination that the Mb is at the second metal LE and upon a determination that the Ma available space at E_VxMa is greater than the minimum allowable space for the Ma and the Mb available space at E_VxMb is greater than the Mb minimum space, jog, by the computer, the design value for the Ma and for the Mb, retarget using the retargeting tables, by the computer, the design value for the Vx and execute, by the computer, the design process or using a third set of predetermined design values, otherwise insert, by the computer, a dummy track into the initial design file layout for the semiconductor structure.

13. The system of claim 10 , wherein the retarget of the Vx comprises retarget, using the retargeting tables, metal below the Vx in a vertical direction to avoid Vx metal shorting.

14. The system of claim 13 , wherein the design application is further configured to:
upon a determination that the resulting design file layout for the semiconductor structure falls outside of a three sigma area for the Vx, re-determine, by the computer, whether the Mb is at the second metal LE, otherwise output, by the computer, the resulting design file layout as a final design file layout for the semiconductor structure.

15. A system for generating a semiconductor structure design comprising:
a memory storing instructions;
a first

Assignees

• IBM

Inventors

• Han Geng
• Shao Dongbing

Classifications

• G03F1/70 Primary

  Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F17/5081

  Physics · mapped topic

• G06F17/5072

  Physics · mapped topic