Efficient survivor memory architecture for successive cancellation list decoding of channel polarization codes

US10523367B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10523367-B2
Application numberUS-201715680661-A
CountryUS
Kind codeB2
Filing dateAug 18, 2017
Priority dateAug 18, 2017
Publication dateDec 31, 2019
Grant dateDec 31, 2019

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A method of storing survivor data generated while decoding channel polarization codes in a memory module includes setting a list size that corresponds to a number of decoder units used to decode the channel polarization codes, inputting a stream of input bits to the decoder units, and sequentially decoding the input bits. Each input bit is decoded using all previous input bits decoded before the each input bit. The method further includes selecting a plurality of survivor bits from among the decoded input bits, and storing the selected survivor bits in the memory module in a binary tree configuration. The number of edges in each level of the binary tree configuration does not exceed the list size.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of storing survivor data generated while decoding channel polarization codes in a memory module, comprising: setting a list size, by a processor, wherein the list size corresponds to a number of decoder units used to decode the channel polarization codes; inputting, under control of the processor, a stream of input bits to the decoder units; sequentially decoding the input bits, by the decoder units, wherein each input bit is decoded using all previous input bits decoded before the each input bit; selecting, by the processor, a plurality of survivor bits from among the decoded input bits; and storing, under control of the processor, the selected survivor bits in the memory module in a binary tree configuration, wherein a number of edges in each level of the binary tree configuration does not exceed the list size. 2. The method of claim 1 , wherein the input bits are sequentially decoded using a list successive cancellation decoding technique. 3. The method of claim 2 , wherein sequentially decoding the input bits using the list successive cancellation decoding technique comprises: computing a plurality of intermediate values, wherein the intermediate values are computed by decoding the each input bit based on a plurality of guesses of the values of the previous input bits decoded before the each input bit, wherein each guess corresponds to a bit value being equal to 0 or being equal to 1. 4. The method of claim 3 , further comprising: selecting a plurality of most probable guesses from among the plurality of guesses using a log-likelihood ratio (LLR) technique; retaining the selected most probable guesses in the memory module; and discarding the guesses from among the plurality of guesses that are not selected as the most probable guesses. 5. The method of claim 3 , wherein storing the selected survivor bits in the memory module in the binary tree configuration comprises: comparing a first group of intermediate values from among the plurality of intermediate values with a second group of intermediate values from among the plurality of intermediate values, wherein the first and second groups are separated into subgroups, each subgroup corresponding to intermediate values obtained during one of a plurality of stages of the sequential decoding process, wherein the comparison is made on a stage-by-stage basis, wherein each stage corresponds to one of the levels of the binary tree configuration; and generating the edges in each of the levels of the binary tree configuration based on the comparison result. 6. The method of claim 5 , wherein generating the edges in each of the levels of the binary tree configuration based on the comparison result comprises: comparing intermediate values from a subgroup of the first group with corresponding intermediate values from a subgroup of the second group; generating only a left edge at a vertex when the compared intermediate values include an intermediate value in the subgroup of the first group that is equal to 1 and an intermediate value in the subgroup of the second group that is equal to 0; generating only a right edge at the vertex when the compared intermediate values include an intermediate value in the subgroup of the first group that is equal to 0 and an intermediate value in the subgroup of the second group that is equal to 1; generating both the left edge and the right edge at the vertex when the compared intermediate values include an intermediate value in the subgroup of the first group that is equal to 1 and an intermediate value in the subgroup of the second group that is equal to 1; and generating neither the left edge nor the right edge at the vertex when the compared intermediate values include an intermediate value in the subgroup of the first group that is equal to 0 and an intermediate value in the subgroup of the second group that is equal to 0, wherein the vertex corresponds to the compared intermediate values. 7. The method of claim 6 , wherein the left edges represent a value of 0 and the right edges represent a value of 1. 8. The method of claim 6 , wherein the left edges represent a value of 1 and the right edges represent a value of 0. 9. The method of claim 5 , wherein generating the edges in each of the levels of the binary tree configuration based on the comparison result comprises: comparing intermediate values from a subgroup of the first group with corresponding intermediate values from a subgroup of the second group; generating only a left edge at a vertex when the compared intermediate values include an intermediate value in the subgroup of the first group that is equal to 0 and an intermediate value in the subgroup of the second group that is equal to 1; generating only a right edge at the vertex when the compared intermediate values include an intermediate value in the subgroup of the first group that is equal to 1 and an intermediate value in the subgroup of the second group that is equal to 0; generating both the left edge and the right edge at the vertex when the compared intermediate values include an intermediate value in the subgroup of the first group that is equal to 1 and an intermediate value in the subgroup of the second group that is equal to 1; and generating neither the left edge nor the right edge at the vertex when the compared intermediate values include an intermediate value in the subgroup of the first group that is equal to 0 and an intermediate value in the subgroup of the second group that is equal to 0, wherein the vertex corresponds to the compared intermediate values. 10. The method of claim 9 , wherein the left edges represent a value of 0 and the right edges represent a value of 1. 11. The method of claim 9 , wherein the left edges represent a value of 1 and the right edges represent a value of 0. 12. The method of claim 5 , wherein generating the edges in each of the levels of the binary tree configuration based on the comparison result comprises: comparing intermediate values from a subgroup of the first group with corresponding intermediate values from a subgroup of the second group; generating only a left edge at a vertex when the compared intermediate values include an intermediate value in the subgroup of the first group that is equal to 1 and an intermediate value in the subgroup of the second group that is equal to 0; generating only a right edge at the vertex when the compared intermediate values include an intermediate value in the subgroup of the first group that is equal to 0 and an intermediate value in the subgroup of the second group that is equal to 1; generating both the left edge and the right edge at the vertex when the compared intermediate values include an intermediate value in the subgroup of the first group that is equal to 0 and an intermediate value in the subgroup of the second group that is equal to 0; and generating neither the left edge nor the right edge at the vertex when the compared intermediate values include an intermediate value in the subgroup of the first group that is equal to 1 and an intermediate value in the subgroup of the second group that is equal to 1, wherein the vertex corresponds to the compared intermediate values. 13. The method of claim 5 , wherein generating the edges in each of the levels of the binary tree configuration based on the comparison result comprises: comparing intermediate values from a subgroup of the first group with corresponding intermediate values from a subgroup of the second group; generating only a left edge at a vertex when the compared intermediate values include an intermediate value in the subgroup of the fir

Assignees

Inventors

Classifications

  • Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms · CPC title

  • Block codes (H04L1/0061, H04L1/0064 take precedence) · CPC title

  • with iterative decoding · CPC title

  • H04L1/0058Primary

    Block-coded modulation · CPC title

  • by updating bit probabilities or hard decisions in an iterative fashion for convergence to a final decoding result · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10523367B2 cover?
A method of storing survivor data generated while decoding channel polarization codes in a memory module includes setting a list size that corresponds to a number of decoder units used to decode the channel polarization codes, inputting a stream of input bits to the decoder units, and sequentially decoding the input bits. Each input bit is decoded using all previous input bits decoded before th…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification H04L1/0058. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 31 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).