Soft decoding of polar codes

Patent metadata

Field	Value
Publication number	US-9317365-B2
Application number	US-201414219279-A
Country	US
Kind code	B2
Filing date	Mar 19, 2014
Priority date	Mar 6, 2014
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

An apparatus having a circuit and an interface to a nonvolatile memory is disclosed. The circuit is configured to (i) read a plurality of bits in a read channel of the nonvolatile memory. The bits are encoded with a polar code. The circuit is also configured to (ii) generate a plurality of probabilities based on a plurality of log likelihood ratio values of the read channel and (iii) decode the bits based on the probabilities.

First claim

The invention claimed is:

1. An apparatus comprising:
an interface configured to process a plurality of read/write operations to/from a memory; and
a control circuit configured to (i) read a plurality of bits in a read channel of the memory, wherein the plurality of bits are encoded with a polar code, (ii) generate a plurality of probabilities of transition errors between two possible states of the plurality of bits based on a plurality of log likelihood ratio values of the read channel of the memory and (iii) decode the plurality of bits based on the plurality of probabilities of transition errors.

2. The apparatus according to claim 1 , wherein the control circuit is further configured to modify one or more bits of the plurality of bits based on the plurality of log likelihood ratio values prior to the plurality of bits being decoded.

3. The apparatus according to claim 2 , wherein (i) a given bit of the plurality of bits is modified to a logical one value where a corresponding log likelihood ratio value of the plurality of log likelihood ratio values is greater than zero and (ii) the given bit is modified to a logical zero value where the corresponding log likelihood ratio value is less than zero.

4. The apparatus according to claim 1 , wherein the plurality of probabilities of transition errors are of a binary symmetric channel.

5. The apparatus according to claim 1 , wherein (i) a given probability of transition errors of the plurality of probabilities of transition errors is generated with a reliable value where a magnitude of a corresponding log likelihood ratio value of the plurality of log likelihood ratio values is large and (ii) the given probability of transition errors is generated with an unreliable value where the magnitude of the corresponding log likelihood ratio value is small.

6. The apparatus according to claim 1 , wherein the plurality of bits are decoded using a list polar decoding.

7. The apparatus according to claim 1 , wherein two or more bits of the plurality of bits have different channel models of the read channel of the memory.

8. The apparatus according to claim 1 , wherein the memory is a flash memory.

9. The apparatus according to claim 1 , wherein the interface and the control circuit are part of a solid-state drive controller.

10. A method for soft decoding of a polar code, comprising the steps of:
reading a plurality of bits in a read channel of a memory, wherein the plurality of bits are encoded with the polar code;
generating a plurality of probabilities of transition errors between two possible states of the plurality of bits based on a plurality of log likelihood ratio values of the read channel of the memory; and
decoding the plurality of bits based on the plurality of probabilities of transition errors.

11. The method according to claim 10 , further comprising the step of:
modifying one or more bits of the plurality of bits based on the plurality of log likelihood ratio values prior to the plurality of bits being decoded.

12. The method according to claim 11 , wherein (i) a given bit of the plurality of bits is modified to a logical one value where a corresponding log likelihood ratio value of the plurality of log likelihood ratio values is greater than zero and (ii) the given bit is modified to a logical zero value where the corresponding log likelihood ratio value is less than zero.

13. The method according to claim 10 , wherein the plurality of probabilities of transition errors are of a binary symmetric channel.

14. The method according to claim 10 , wherein (i) a given probability of transition errors of the plurality of probabilities of transition errors is generated with a reliable value where a magnitude of a corresponding log likelihood ratio value of the plurality of log likelihood ratio values is large and (ii) the given probability of transition errors is generated with an unreliable value where the magnitude of the corresponding log likelihood ratio value is small.

15. The method according to claim 10 , wherein the plurality of bits are decoded using a list polar decoding.

16. The method according to claim 10 , wherein two or more bits of the plurality of bits have different channel models of the read channel of the memory.

17. The method according to claim 10 , wherein the memory is a flash memory.

18. The method according to claim 10 , wherein the steps are performed in a solid-state drive controller.

19. An apparatus comprising:
a memory configured to store data; and
a controller configured to (i) process a plurality of input/output requests to read/write to/from the memory, (ii) read a plurality of bits in a read channel of the memory, wherein the plurality of bits are encoded with a polar code, (iii) generate a plurality of probabilities of transition errors between two possible states of the plurality of bits based on a plurality of log likelihood ratio values of the read channel of the memory and (iv) decode the plurality of bits based on the plurality of probabilities of transition errors.

20. The apparatus according to claim 19 , wherein the memory and the controller are part of a solid-state drive.

Assignees

• Seagate Technology Llc

Inventors

• Alhussien Abdelhakim S
• Haratsch Erich F
• Li Yue

Classifications

• H04L1/0054

  Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms · CPC title

• H03M13/13 Primary

  Linear codes · CPC title

• G06F11/1076 Primary

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title

• H03M13/453

  wherein the candidate code words are obtained by an algebraic decoder, e.g. Chase decoding · CPC title

• H03M13/45

  Soft decoding, i.e. using symbol reliability information (H03M13/41 takes precedence) · CPC title