Method for laterally trimming a hardmask
US-9779952-B2 · Oct 3, 2017 · US
MTJ CD variation by HM trimming
US10522751B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10522751-B2 |
| Application number | US-201815986183-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 22, 2018 |
| Priority date | May 22, 2018 |
| Publication date | Dec 31, 2019 |
| Grant date | Dec 31, 2019 |
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Abstract
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A MTJ stack is deposited on a bottom electrode. A metal hard mask is deposited on the MTJ stack and a dielectric mask is deposited on the metal hard mask. A photoresist pattern is formed on the dielectric mask, having a critical dimension of more than about 65 nm. The dielectric and metal hard masks are etched wherein the photoresist pattern is removed. The dielectric and metal hard masks are trimmed to reduce their critical dimension to 10-60 nm and to reduce sidewall surface roughness. The dielectric and metal hard masks and the MTJ stack are etched wherein the dielectric mask is removed and a MTJ device is formed having a small critical dimension of 10-60 nm, and having further reduced sidewall surface roughness.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for etching a magnetic tunneling junction (MTJ) structure comprising: depositing a MTJ stack on a bottom electrode; depositing a conductive hard mask on said MTJ stack; depositing a dielectric mask on said conductive hard mask; forming a photoresist pattern on said dielectric mask, having a critical dimension of about 40-115 nm; first etching said dielectric and conductive hard masks wherein said photoresist pattern is removed; thereafter…
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Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- G11C11/161Primary
Physics · mapped topic
- H01L43/12Primary
Electricity · mapped topic
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- What does patent US10522751B2 cover?
- A MTJ stack is deposited on a bottom electrode. A metal hard mask is deposited on the MTJ stack and a dielectric mask is deposited on the metal hard mask. A photoresist pattern is formed on the dielectric mask, having a critical dimension of more than about 65 nm. The dielectric and metal hard masks are etched wherein the photoresist pattern is removed. The dielectric and metal hard masks are t…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification G11C11/161. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Dec 31 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).