Methods for fabricating anode shorted field stop insulated gate bipolar transistor

Patent metadata

Field	Value
Publication number	US-10522666-B2
Application number	US-201815917415-A
Country	US
Kind code	B2
Filing date	Mar 9, 2018
Priority date	Jul 27, 2011
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.

First claim

What is claimed is:

1. A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT), comprising:
a) forming one or more insulated gate bipolar transistors (IGBT) component cells within a top surface of an epitaxial layer of a first conductivity type;
b) thinning a back surface of a substrate on which the epitaxial layer is formed to a desired thickness, wherein the substrate is of a second conductivity type that is opposite the first conductivity type;
c) performing a blanket implant of the first conductivity type to the back surface of the substrate to form a field stop layer, wherein a concentration of charge carriers in the field stop layer is greater than that of the epitaxial layer;
d) selectively implanting first semiconductor regions of a second conductivity type that is opposite the first conductivity type within a back surface of the field stop layer using a first shadow mask, wherein a concentration of charge carriers in the first semiconductor regions is greater than that of the field stop layer;
e) selectively implanting second semiconductor regions of the first conductivity type within a back surface of the field stop layer using a second shadow mask, wherein a concentration of charge carriers in the second semiconductor regions is greater than that of the field stop layer; and
f) laser activating the first and second semiconductor regions;
g) depositing a metal layer to a back surface of the first and second semiconductor regions.

2. The method of claim 1 , wherein the epitaxial layer is doped n−, the field stop layer is doped n, the first semiconductor regions are doped p+ and the second semiconductor regions are doped n+.

3. The method of claim 2 , wherein the first shadow mask and the second shadow mask are complementary.

4. The method of claim 2 , wherein a width of the first semiconductor regions of the second conductivity type is much larger than a width of second semiconductor regions of the first conductivity type.

5. The method of claim 1 , wherein the blanket implant in c) is a Phosphorous implant with a concentration between 1×10 13 /cm 3 and 2×10 13 /cm 3 performed at 100-300 keV.

Assignees

• Alpha & Omega Semiconductor

Inventors

• Bhalla Anup
• Bobde Madhur
• Ding Yongping
• Zhang Xiaotian
• Ho Yueh-Se

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22

  using masks · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10W10/031

  of isolation regions comprising PN junctions · CPC title