Semiconductor device and manufacturing method therefor

Patent metadata

Field	Value
Publication number	US-10522651-B2
Application number	US-201715823029-A
Country	US
Kind code	B2
Filing date	Nov 27, 2017
Priority date	Dec 1, 2016
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method may include: providing a semiconductor structure, where the semiconductor structure includes a semiconductor fin and an interlayer dielectric layer covering the semiconductor fin, the interlayer dielectric layer having an opening exposing a part of the semiconductor fin; forming a data storage layer at a bottom portion and a side surface of the opening; and filling a conductive material layer in the opening on the data storage layer. The present disclosure facilitate the manufacturing process of the semiconductor device and improves processing compatibility with the CMOS technology.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:
providing a semiconductor structure, wherein the semiconductor structure comprises: a semiconductor fin and an interlayer dielectric layer covering the semiconductor fin, the interlayer dielectric layer having an opening exposing a first part of the semiconductor fin;
forming a data storage layer at a bottom portion and a side surface of the opening; and
filling a conductive material layer in the opening directly on the data storage layer.

2. The method according to claim 1 , wherein providing a semiconductor structure comprises:
providing an initial structure, wherein the initial structure comprises: a semiconductor fin, an interlayer dielectric layer covering the semiconductor fin, and a first dummy gate located in the interlayer dielectric layer, wherein an upper surface of the first dummy gate is flush with an upper surface of the interlayer dielectric layer; and
removing the first dummy gate, so as to form the opening exposing the first part of the semiconductor fin.

3. The method according to claim 2 , wherein:
the first dummy gate is separated from the semiconductor fin; and
removing the first dummy gate comprises:
removing the first dummy gate to form an opening; and
enlarging the opening by using a first etching process, so as to expose the first part of the semiconductor fin.

4. The method according to claim 2 , wherein:
the initial structure further comprises: a trench isolation portion abutting a side surface of the semiconductor fin; and
the first dummy gate is located above the trench isolation portion.

5. The method according to claim 2 , wherein a side surface of the semiconductor fin is an inclined surface, and the first part of the semiconductor fin exposed by the opening is within the inclined surface.

6. The method according to claim 2 , further comprising forming, in the interlayer dielectric layer, a gate structure located on the semiconductor fin.

7. The method according to claim 6 , wherein forming the gate structure comprises:
forming, in the interlayer dielectric layer, a second dummy gate located on the semiconductor fin, wherein an upper surface of the second dummy gate is flush with the upper surface of the interlayer dielectric layer;
removing the second dummy gate, so as to form an open trench exposing a second part of the semiconductor fin; and
forming the gate structure in the open trench.

8. The method according to claim 7 , wherein before removing the first dummy gate to form the opening, the method further comprises forming a first patterned mask layer on the interlayer dielectric layer covering the second dummy gate and exposing the first dummy gate; and
wherein after removing the first dummy gate to form the opening and before forming the data storage layer, the method further comprises removing the first patterned mask layer.

9. The method according to claim 7 , wherein removing the second dummy gate comprises:
forming a second patterned mask layer on the interlayer dielectric layer covering the data storage layer and the conductive material layer and exposing the second dummy gate;
removing the second dummy gate using a second etching process, so as to form the open trench exposing the second part of the semiconductor fin; and
removing the second patterned mask layer.

10. The method according to claim 1 , wherein the data storage layer comprises a transition metal oxide (TMO).

11. The method according to claim 1 , further comprising forming a conductive contact on the conductive material layer.

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp
• Semiconductor Mfg International Shanghai Corp
• Semiconductor Mfg International Beijing Corp

Inventors

• Chen Zhuofan
• Zhang Haiyang

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L29/66795

  Electricity · mapped topic

• H01L29/42364

  Electricity · mapped topic

• H01L29/66545 Primary

  Electricity · mapped topic