Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication

Patent metadata

Field	Value
Publication number	US-10522629-B2
Application number	US-201715835162-A
Country	US
Kind code	B2
Filing date	Dec 7, 2017
Priority date	May 17, 2005
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

A method of forming a semiconductor structure includes forming an opening in a dielectric layer, forming a recess in an exposed part of a substrate, and forming a lattice-mismatched crystalline semiconductor material in the recess and opening.

First claim

What is claimed is:

1. A method of forming a semiconductor device comprising:
forming a dielectric material over a substrate comprising a first crystalline material;
patterning the dielectric material to expose a portion of the substrate;
forming a recess in the exposed portions of the substrate;
forming a second crystalline material protruding from the recess, wherein a first portion of the second crystalline material is disposed within the recess, wherein a second portion of the second crystalline material extends over a top surface of the dielectric material, wherein the second crystalline material is lattice mismatched to the first crystalline material;
forming a photonic device on the second portion of the second crystalline material;
removing the substrate to expose the first portion of the second crystalline material and the second portion of the second crystalline material; and
removing an end portion of the exposed first portion of the second crystalline material to form ridges comprising the remaining first portion of the second crystalline material, the ridges protruding from the second portion of the second crystalline material.

2. The method of claim 1 , further comprising forming a third crystalline material within the recess prior to forming the second crystalline material, wherein the third crystalline material is lattice mismatched to the first crystalline material and the second crystalline material.

3. The method of claim 1 further comprising removing the dielectric material after removing the end portion of the exposed first portion of the second crystalline material.

4. The method of claim 1 , wherein a spacing between adjacent ridges is less than or equal to a visible light wavelength.

5. The method of claim 1 , wherein a width of one or more ridges is less than or equal to a visible light wavelength.

6. The method of claim 1 , further comprising forming a metal contact on at least one ridge.

7. The method of claim 1 , wherein removing an end portion of the exposed first portion of the second crystalline material comprises performing a chemical-mechanical polish (CMP).

8. The method of claim 1 , wherein forming the photonic device comprises forming a light-emitting diode (LED).

9. The method of claim 1 , wherein the exposed first portion of the second crystalline semiconductor material comprises a non-planar surface.

10. A method comprising:
forming a dielectric layer over a first surface of a semiconductor substrate, the thickness of the dielectric layer over the first surface being a first distance, the semiconductor substrate comprising a first semiconductor material;
forming a plurality of openings in the dielectric layer;
etching the first surface of the semiconductor substrate to form a plurality of grooves extending a second distance below the first surface of the semiconductor substrate;
depositing a second semiconductor material in the grooves, the second semiconductor material extending above the first surface of the semiconductor substrate, the second semiconductor material different from the first semiconductor material;
forming a photonic semiconductor structure on the second semiconductor material;
etching the semiconductor substrate to expose the second semiconductor material;
removing a first portion of the second semiconductor material, the first portion of the semiconductor material extending between the first distance and a sum of the first distance and the second distance into the exposed second semiconductor material, a remaining second portion of the second semiconductor material forming a plurality of raised features.

11. The method of claim 10 , further comprising etching the dielectric layer after etching the semiconductor substrate.

12. The method of claim 10 , wherein the plurality of raised features comprises a two-dimensional array of raised features.

13. The method of claim 10 , wherein forming the photonic semiconductor structure comprises depositing a third semiconductor material on the second semiconductor material, the third semiconductor material different from the second semiconductor material.

14. The method of claim 10 , further comprising forming a metal layer on the photonic semiconductor structure.

15. The method of claim 10 , wherein the plurality of grooves comprise (111) surfaces of the first semiconductor material.

16. The method of claim 10 , further comprising forming an etch-stop on the second semiconductor material.

17. A method comprising:
forming a crystalline semiconductor substrate comprising a plurality of ridges protruding a first height from a first surface, wherein a width of each ridge is less than or equal to a visible light wavelength and wherein a spacing between adjacent ridges is less than or equal to a visible light wavelength;
recessing the plurality of ridges, wherein after the recessing, the plurality of ridges protrude a second height from the first surface that is less than the first height; and
after recessing the plurality of ridges, forming a photonic structure on a second surface of the crystalline semiconductor substrate.

18. The method of claim 17 , further comprising forming a metal contact on the plurality of ridges.

19. The method of claim 18 , wherein the metal contact conforms to at least one ridge of the plurality of ridges.

20. The method of claim 17 , further comprising forming a metal layer on a surface of the photonic structure that is opposite the crystalline semiconductor substrate.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Li Jizhong
• Lochtefeld Anthony J

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H10P14/3466

  Crystal orientation · CPC title

• H10P14/3402

  characterised by the chemical composition · CPC title

• H10P14/2926

  Crystal orientations · CPC title