Method for forming a three-dimensional memory device

Patent metadata

Field	Value
Publication number	US-10522561-B2
Application number	US-201816047178-A
Country	US
Kind code	B2
Filing date	Jul 27, 2018
Priority date	Aug 23, 2017
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

Embodiments of a method for forming a three-dimensional (3D) memory devices are disclosed. The method can comprise forming a device wafer including: forming a first channel hole penetrating a first alternating layer stack of a device wafer, forming an epitaxial layer on a bottom of the first channel hole, and forming a first channel layer on a sidewall of the first channel hole. The method can further comprise forming at least one connecting wafer, each connecting wafer including a second channel hole penetrating a second alternating layer stack without an epitaxial layer on a bottom of the second channel hole; and bonding the at least one connecting wafer and the device wafer, such that a second channel layer on a sidewall of the second channel hole in each connecting wafer is electrically connected with the first channel layer in the device wafer.

First claim

What is claimed is:

1. A method for forming a channel hole structure in a three-dimensional (3D) memory device, comprising:
forming a device wafer including:
forming a first channel hole penetrating a first alternating layer stack of a device wafer,
forming an epitaxial layer on a bottom of the first channel hole, and
forming a first channel layer on a sidewall of the first channel hole;

forming at least one connecting wafer, wherein each connecting wafer includes a second channel hole penetrating a second alternating layer stack without an epitaxial layer on a bottom of the second channel hole; and
bonding the at least one connecting wafer and the device wafer, such that a second channel layer on a sidewall of the second channel hole in each connecting wafer is electrically connected with the first channel layer in the device wafer.

2. The method of claim 1 , further comprising:
forming a first interconnect surface including a top surface of a first channel connection structure on the device wafer, a width of the first channel connection structure being larger than a thickness of the first channel layer;
forming a second interconnect surface including a top surface of a second channel connection structure on the connecting wafer, a width of the second channel connection structure being larger than a thickness of the second channel layer; and
bonding a first connecting wafer and the device wafer, including:
aligning the first channel connection structure of the device wafer and the second channel connection structure of the first connecting wafer, and
bonding the first interconnect surface of the device wafer to the second interconnect surface of the first connecting wafer such that the first channel connection structure is in direct contact with the second channel connection structure.

3. The method of claim 2 , wherein forming the device wafer further comprises:
forming a first alternating dielectric stack and a first insulating connection layer on a first substrate;
forming the first channel hole penetrating the first insulating connection layer and the first alternating dielectric stack;
after forming the epitaxial layer on a bottom of the first channel hole, forming a first functional layer to cover a sidewall of the first channel hole;
forming the first channel layer covering the first functional layer and in contact with the epitaxial layer; and
forming the first channel connection structure above the first functional layer, the first channel connection structure being in contact with the first channel layer.

4. The method of claim 3 , wherein forming the first functional layer comprises:
forming a first barrier layer on the sidewall of the first channel hole for blocking an outflow of electronic charges;
forming a first storage layer on a surface of the first barrier layer for storing electronic charges during operation of the 3D memory device; and
forming a first tunneling layer on a surface of the first storage layer for tunneling electronic charges.

5. The method of claim 4 , wherein forming the first channel connection structure comprises:
forming a first channel connection layer on the first insulating connection layer, the first channel connection layer being in contact with the first channel layer;
forming a first filling structure to fill the first channel hole; and
patterning the first channel connection layer to remove a portion of the first channel connection layer to expose the first storage layer, the remaining portion of the first channel connection layer that is above the first tunneling layer and the first channel layer being the first channel connection structure.

6. The method of claim 5 , wherein forming the first interconnect surface comprises:
after patterning the first channel connection layer, removing an upper portion of the first storage layer; and
refilling the first insulation connection layer and the first filling structure, such that top surfaces of the first insulation connection layer and the first filling structure are in level with the top surface of the first channel connection structure.

7. The method of claim 3 , wherein forming each connecting wafer comprises:
forming a second alternating dielectric stack on a second substrate;
forming the second channel hole penetrating the second alternating dielectric stack;
forming a second functional layer to cover a sidewall of the second channel hole;
forming the second channel layer covering the second functional layer;
forming a second filling structure to fill the second channel hole; and
forming the second channel connection structure above the second functional layer, the second channel connection structure being in contact with the second channel layer.

8. The method of claim 7 , wherein forming the second functional layer comprises:
forming a second barrier layer on the sidewall of the second channel hole for blocking an outflow of electronic charges;
forming a second storage layer on a surface of the second barrier layer for storing electronic charges during operation of the 3D memory device; and
forming a second tunneling layer on a surface of the second storage layer for tunneling electronic charges.

9. The method of claim 8 , wherein forming each connecting wafer further comprises:
before forming the second channel connection structure, removing an upper portion of the first storage layer; and
forming a second insulation connection layer to cover top surfaces of the second alternating dielectric stack and the second functional layer.

10. The method of claim 9 , wherein forming the second channel connection structure comprises:
forming a second channel connection layer on the second insulating connection layer, the second channel connection layer being in contact with the second channel layer and insulated with the second storage layer; and
patterning the second channel connection layer to remove a portion of the second channel connection layer, the remaining portion of the second channel connection layer that is above the second tunneling layer and the second channel layer being the second channel connection structure.

11. The method of claim 7 , wherein bonding the first connecting wafer and the device wafer further comprises:
aligning and bonding one connecting wafer and the device wafer in a face-to-face manner to form a bonded structure;
removing a portion of the bonded structure including the second substrate to expose the second channel layer and the second filling structure; and
forming a channel plug on the second filling structure, the channel plug being in contact with the second channel layer.

12. The method of claim 7 , wherein bonding the at least one connecting wafer and the device wafer further comprises:
aligning and bonding the first connecting wafer and the device wafer in a face-to-face manner to form a two-deck bonded structure;
removing a portion of the two-deck bonded structure including the second substrate to expose the second channel layer;
forming a third channel connection structure in contact with the second channel layer, a width of the third channel connection structure being larger than the thickness of the second channel layer; and
forming a third interconnect surface of the two-deck structure including a top surface of the third channel connection structure.

13. The method of claim 12 , wherein bonding the at least one connecting wafer and the device wafer further comprises:
aligning and bonding a second connecting wafer and the two-deck bonded structure in a face-to-face manner to form a three-deck bonded structure, such that the second channel connection st

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Zhang Kun
• Liu Fandong
• Xia Zhiliang

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H01L27/11556

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic