Uniform gate dielectric for DRAM device

Patent metadata

Field	Value
Publication number	US-10522549-B2
Application number	US-201815898501-A
Country	US
Kind code	B2
Filing date	Feb 17, 2018
Priority date	Feb 17, 2018
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

Provided herein are approaches for forming a gate dielectric layer for a DRAM device, the method including providing a substrate having a recess formed therein, the recess including a sidewall surface and a bottom surface. The method may further include performing an ion implant into just the bottom surface of the recess, and forming a gate dielectric layer along the bottom surface of the recess and along the sidewall surface of the recess. Once formed, a thickness of the gate dielectric layer along the sidewall surface is approximately the same as a thickness of the gate dielectric layer along the bottom surface of the recess. In some embodiments, the gate dielectric layer is thermally grown within the recess. In some embodiments, the ion implant is performed after a mask layer atop the substrate is removed.

First claim

What is claimed is:

1. A method of forming a dynamic random-access memory device (DRAM) device, the method comprising:
providing a substrate having a recess formed therein, the recess including a sidewall surface and a bottom surface;
performing an ion implant into just the bottom surface of the recess to form an oxide layer on the bottom surface; and
forming a gate dielectric layer over the oxide layer along the bottom surface of the recess and along the sidewall surface of the recess, wherein a thickness of the gate dielectric layer along the sidewall surface is approximately the same as a thickness of the oxide layer combined with the gate dielectric layer along the bottom surface of the recess.

2. The method of claim 1 , further comprising:
patterning a mask layer over substrate; and
etching the substrate remaining exposed by an opening of the mask layer to form the recess.

3. The method of claim 2 , further comprising removing the mask layer from atop the substrate, wherein the ion implant is performed after the mask layer is removed.

4. The method of claim 1 , wherein the gate dielectric layer is an oxide layer thermally grown within the recess.

5. The method of claim 1 , wherein an ion species of the ion implant is at least one of: germanium, fluorine, and oxygen.

6. The method of claim 1 , further comprising performing the ion implant into a top surface of the substrate.

7. The method of claim 6 , further comprising performing the ion implant at an angle approximately perpendicular to the top surface of the substrate.

8. The method of claim 1 , wherein the ion implant does not impact the sidewall surface of the recess.

9. A method of forming a buried word line transistor of a dynamic random-access memory device, the method comprising:
forming a plurality of buried channels recessed below a top surface of a substrate, each of the plurality of buried channels including a sidewall surface and a bottom surface;
forming an oxide layer on the bottom surface of each of the plurality of buried channels by performing an ion implant into just the bottom surface of each of the plurality of buried channels; and
forming a gate dielectric layer over the oxide layer along the bottom surface and along the sidewall surface of each of the plurality of buried channels after the ion implant is performed, wherein a thickness of the gate dielectric layer along the sidewall surface of each of the plurality of buried channels is approximately the same as a thickness of the oxide layer combined with the gate dielectric layer along the bottom surface of the recess.

10. The method of claim 9 , further comprising:
patterning a mask layer over substrate; and
etching the substrate remaining exposed by the mask layer to form each of the plurality of buried channels.

11. The method of claim 10 , further comprising removing the mask layer from atop the substrate, wherein the ion implant is performed after the mask layer is removed.

12. The method of claim 9 , wherein the gate dielectric layer is an oxide layer thermally grown along the top surface of the substrate and within each of the plurality of buried channels.

13. The method of claim 9 , wherein a species of the ion implant is at least one of: germanium, fluorine, and oxygen.

14. The method of claim 9 , wherein the ion implant further impacts the top surface of the substrate.

15. The method of claim 14 , further comprising performing the ion implant at an angle approximately perpendicular to the top surface of the substrate.

16. The method of claim 9 , wherein the ion implant does not impact the sidewall surface of each of the plurality of buried channels.

17. A method of forming a uniform gate oxide layer of a dynamic random-access memory device (DRAM) device, the method comprising:
etching a plurality of buried channels in a substrate, each of the plurality of buried channels including a sidewall surface and a bottom surface;
performing an ion implant into just the bottom surface of each of the plurality of buried channel to form an oxide layer on the bottom surface; and
forming a gate dielectric layer over the oxide layer along the bottom surface and along the sidewall surface of each of the plurality of buried channels after the ion implant is performed, wherein a thickness of the gate dielectric layer along the sidewall surface of each of the plurality of buried channels is approximately the same as a thickness of the oxide layer combined with the gate dielectric layer along the bottom surface of the recess.

18. The method of claim 17 , further comprising:
patterning a mask layer over substrate; and
etching the substrate remaining exposed by the mask layer to form each of the plurality of buried channels.

19. The method of claim 18 , further comprising removing the mask layer from atop the substrate, wherein the ion implant is performed after the mask layer is removed, and wherein the ion implant forms the oxide layer along just the bottom surface of each of the plurality of buried channels.

20. The method of claim 17 , further comprising thermally growing the gate oxide layer over all exposed surfaces of the substrate including within each of the plurality of buried channels.

Assignees

• Varian Semiconductor Equipment Ass Inc

Inventors

• Guo Baonian
• Zhang Qintao

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P14/6502

  of treatments performed before formation of the materials · CPC title

• H10P14/6304

  Formation by oxidation, e.g. oxidation of the substrate · CPC title

• H10P14/6302

  Non-deposition formation processes · CPC title

• H10D64/01348 Primary

  with substrate doping, e.g. N, Ge or C implantation, before formation of the insulator · CPC title