Stacked field-effect transistors (FETs) with shared and non-shared gates

Patent metadata

Field	Value
Publication number	US-10522419-B2
Application number	US-201916374114-A
Country	US
Kind code	B2
Filing date	Apr 3, 2019
Priority date	Nov 2, 2017
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

A semiconductor device includes a plurality of stacked gate regions spaced apart from each other on a substrate, a plurality of first epitaxial source/drain regions between the plurality of stacked gate regions, wherein the first epitaxial source/drain regions extend from sides of the plurality of stacked gate regions in a first doped region, a plurality of second epitaxial source/drain regions between the plurality of stacked gate regions and positioned over the first epitaxial source/drain regions, wherein the second epitaxial source/drain regions extend from sides of the plurality of stacked gate regions in a second doped region, and a contact region extending through a second epitaxial source/drain region of the plurality of second epitaxial source/drain regions to a first epitaxial source/drain region of the plurality of first epitaxial source/drain regions.

First claim

We claim:

1. A method for manufacturing a semiconductor device, comprising:
forming a stacked configuration of silicon germanium and silicon layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a silicon layer stacked on a silicon germanium layer;
patterning the stacked configuration into a plurality of patterned stacks spaced apart from each other;
covering exposed sides of the silicon germanium layers in the plurality of patterned stacks with a dielectric;
growing a plurality of source/drain regions between the plurality of patterned stacks, wherein the source/drain regions are grown from exposed sides of the silicon layers in the plurality of patterned stacks;
selectively removing the silicon germanium layers from the plurality of patterned stacks; and
replacing the removed silicon germanium layers with respective gate regions.

2. The method according to claim 1 , further comprising recessing the source/drain regions to a lower height between the plurality of patterned stacks corresponding to a first type doped region, wherein the source/drain regions are doped with a first type dopant.

3. The method according to claim 2 , further comprising forming respective dielectric layers on the recessed source/drain regions.

4. The method according to claim 3 , further comprising growing a plurality of additional source/drain regions between the plurality of patterned stacks, wherein the plurality of additional source/drain regions are grown from exposed sides of the silicon layers in the plurality of patterned stacks positioned above the respective dielectric layers.

5. The method according to claim 4 , wherein the plurality of additional source/drain regions correspond to a second type doped region, and the plurality of additional source/drain regions are doped with a second type dopant different from the first type dopant.

6. The method according to claim 5 , further comprising forming a contact region to a source/drain region of the plurality of source/drain regions between the plurality of patterned stacks, wherein the contact region extends through an additional source/drain region of the plurality of additional source/drain regions to the source/drain region of the plurality of source/drain regions.

7. The method according to claim 5 , wherein a first portion of the respective gate regions corresponds to the first type doped region and a second portion of the respective gate regions stacked on the first portion corresponds to the second type doped region.

8. The method according to claim 7 , wherein the first and second portions of the respective gate regions comprise different materials from each other, which respectively correspond to the first and second type doped regions.

9. The method according to claim 5 , further comprising:
forming a contact region to a source/drain region of the plurality of source/drain regions between the plurality of patterned stacks; and
forming a contact region to an additional source/drain region of the plurality of additional source/drain regions doped which is stacked on and electrically isolated from a portion of the contact region to the source/drain region of the plurality of source/drain regions.

10. The method according to claim 1 , further comprising covering exposed sides of a portion of the silicon layers in the plurality of patterned stacks with the dielectric prior to growing the plurality of source/drain regions between the plurality of patterned stacks.

11. The method according to claim 10 , wherein the portion of the silicon layers whose sides are covered corresponds to a dummy device region.

12. The method according to claim 11 , further comprising forming a contact region to a source/drain region of the plurality of source/drain regions between the plurality of patterned stacks, wherein the contact region extends through the dummy device region to the source/drain region of the plurality of source/drain regions.

13. The method according to claim 12 , wherein the plurality of source/drain regions correspond to an active device region located under the dummy device region.

14. The method according to claim 11 , wherein a first portion of the respective gate regions corresponds to an active device region and a second portion of the respective gate regions stacked on the first portion corresponds to the dummy device region.

15. The method according to claim 10 , wherein the portion of the silicon layers whose sides are covered is located above the silicon layers from which the plurality of source/drain regions are grown.

16. The method according to claim 1 , further comprising forming a plurality of dummy gates spaced apart from each other on the stacked configuration, wherein the plurality of dummy gates cover a portion of the stacked configuration in a channel region.

17. A method for manufacturing a semiconductor device, comprising:
forming a stacked configuration of first and second semiconductor layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer;
patterning the stacked configuration into a plurality of patterned stacks spaced apart from each other;
covering exposed sides of the first semiconductor layers in the plurality of patterned stacks with a dielectric;
growing a plurality of source/drain regions between the plurality of patterned stacks, wherein the source/drain regions are grown from exposed sides of the second semiconductor layers in the plurality of patterned stacks;
selectively removing the first semiconductor layers from the plurality of patterned stacks; and
replacing the removed first semiconductor layers with respective gate regions.

18. The method according to claim 17 , further comprising recessing the source/drain regions to a lower height between the plurality of patterned stacks corresponding to a first type doped region, wherein the source/drain regions are doped with a first type dopant.

19. The method according to claim 18 , further comprising forming respective dielectric layers on the recessed source/drain regions.

20. The method according to claim 19 , further comprising growing a plurality of additional source/drain regions between the plurality of patterned stacks, wherein the plurality, of additional source/drain regions are grown from exposed sides of the silicon layers in the plurality of patterned stacks positioned above the respective dielectric layers.

Assignees

• IBM

Inventors

• Ando Takashi
• Hashemi Pouya
• Lee Choonghyun
• Reznicek Alexander
• Zhang Jingyun

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/242

  of Group IV materials · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/401

  Electricity · mapped topic