Method of creating aligned vias in ultra-high density integrated circuits

Patent metadata

Field	Value
Publication number	US-10522394-B2
Application number	US-201816106205-A
Country	US
Kind code	B2
Filing date	Aug 21, 2018
Priority date	Sep 25, 2017
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

A method of forming vias aligned with metal lines in an integrated circuit is provided. The method includes: forming a stacked dielectric, capped, hard mask, and first film and photoresist layers; patterning first photoresist layer to provide metal line masks; etching hard mask layer based on patterned first photoresist layer to form metal line masks; ashing first photoresist and film layers; forming second film and photoresist layers on hard mask layer; patterning second photoresist layer to form via masks across opposing sides of metal line masks; etching second film and capped layers based on patterned second photoresist layer; ashing second photoresist and film layers; etching dielectric and capped layers based on a pattern of hard mask layer to provide via and metal line regions; etching hard mask and capped layers; and performing dual damascene process operations to form vias and metal lines in via and metal line regions.

First claim

What is claimed is:

1. A method of forming vias aligned with metal lines in an integrated circuit, the method comprising:
forming a stack including a first plurality of layers, wherein the first plurality of layers comprise a dielectric layer, a capped layer, a hard mask layer, a first film layer, and a first photoresist layer;
patterning the first photoresist layer to provide metal line masks;
etching the hard mask layer based on the patterned first photoresist layer to form metal line masks in the hard mask layer;
ashing the first photoresist layer and the first film layer;
forming a second plurality of layers on the hard mask layer, wherein the second plurality of layers include a second film layer and a second photoresist layer;
patterning the second photoresist layer to form via masks, wherein the via masks extend across opposing sides of the metal line masks;
etching the second film layer and the capped layer based on the patterned second photoresist layer;
ashing the second photoresist layer and the second film layer;
etching the dielectric layer and the capped layer based on a pattern of the hard mask layer to provide a plurality of via regions and a plurality of metal line regions;
etching the hard mask layer and the capped layer; and
performing a plurality of dual damascene process operations to form the vias and the metal lines in the plurality of via regions and the plurality of metal line regions.

2. The method of claim 1 , wherein the forming of the first plurality of layers comprises:
forming the dielectric layer;
forming the capped layer on the dielectric layer;
forming the hard mask layer on the capped layer;
forming the first film layer on the hard mask layer; and
forming the first photoresist layer on the first film layer.

3. The method of claim 1 , wherein the first film layer comprises at least one of amorphous silicon or an anti-reflective coating film.

4. The method of claim 1 , wherein the hard mask layer is formed of titanium nitride.

5. The method of claim 1 , wherein:
the hard mask layer is used as a first mask layer to mask the capped layer; and
the capped layer is used as a second mask layer to mask the dielectric layer.

6. The method of claim 1 , wherein the forming of the second plurality of layers comprises:
forming the second film layer on the hard mask layer; and
forming the second photoresist layer on the second film layer.

7. The method of claim 1 , wherein the second film layer comprises at least one of amorphous silicon or an anti-reflective coating film.

8. The method of claim 1 , wherein the second film layer and the capped layer are anisotropically etched based on the patterned second photoresist layer.

9. The method of claim 1 , wherein the etching of the dielectric layer and the capped layer comprises etching the dielectric layer based on a pattern of the hard mask layer and a pattern of the capped layer.

10. The method of claim 9 , wherein the etching of the dielectric layer and the capped layer comprises:
subsequent to etching the dielectric layer, etching the capped layer based on a pattern of the hard mask layer; and
subsequent to etching the capped layer, etching the dielectric layer based on a pattern of the hard mask layer and a pattern of the capped layer.

11. The method of claim 1 , wherein the dielectric layer and the capped layer are anisotropically etched based on the pattern of the hard mask layer.

12. The method of claim 1 , further comprising, prior to forming the dielectric layer, forming an interconnect layer and forming an etch stop layer on the interconnect layer,
wherein subsequent to etching the dielectric layer and prior to performing the plurality of dual damascene process operations, etching the etch stop layer until a top surface of the interconnect layer is reached.

13. The method of claim 1 , wherein the plurality of dual damascene process operations comprise:
forming a barrier layer in each of the plurality of via regions and the plurality of metal line regions;
forming a seed layer on each of the barrier layers; and
electroplating the seed layers.

14. A processing system for processing a substrate and forming vias aligned with metal lines in an integrated circuit, wherein the processing system comprises:
a processor;
a memory; and
one or more applications stored in the memory and including instructions, which are executable by the processor to
form a stack including a first plurality of layers, wherein the first plurality of layers comprise a dielectric layer, a capped layer, a hard mask layer, a first film layer, and a first photoresist layer,
pattern the first photoresist layer to provide metal line masks,
etch the hard mask layer based on the patterned first photoresist layer to form metal line masks in the hard mask layer,
ash the first photoresist layer and the first film layer,
form a second plurality of layers on the hard mask layer, wherein the second plurality of layers include a second film layer and a second photoresist layer,
pattern the second photoresist layer to form via masks, wherein the via masks extend across opposing sides of the metal line masks,
etch the second film layer and the capped layer based on the patterned second photoresist layer,
ash the second photoresist layer and the second film layer,
etch the dielectric layer and the capped layer based on a pattern of the hard mask layer to provide a plurality of via regions and a plurality of metal line regions,
etch the hard mask layer and the capped layer, and
perform a plurality of dual damascene process operations to form the vias and the metal lines in the plurality of via regions and the plurality of metal line regions.

15. The processing system of claim 14 , wherein the forming of the first plurality of layers comprises:
forming the dielectric layer;
forming the capped layer on the dielectric layer;
forming the hard mask layer on the capped layer;
forming the first film layer on the hard mask layer; and
forming the first photoresist layer on the first film layer.

16. The processing system of claim 14 , wherein:
the hard mask layer is used as a first mask layer to mask the capped layer; and
the capped layer is used as a second mask layer to mask the dielectric layer.

17. The processing system of claim 14 , wherein the forming of the second plurality of layers comprises:
forming the second film layer on the hard mask layer; and
forming the second photoresist layer on the second film layer.

18. The processing system of claim 14 , wherein:
the second film layer and the capped layer are anisotropically etched based on the patterned second photoresist layer; and
the dielectric layer and the capped layer are anisotropically etched based on the pattern of the hard mask layer.

19. The processing system of claim 14 , wherein the etching of the dielectric layer and the capped layer comprises:
etching the dielectric layer based on a pattern of the hard mask layer and a pattern of the capped layer;
subsequent to etching the dielectric layer, etching the capped layer based on a pattern of the hard mask layer; and
subsequent to etching the capped layer, etching the dielectric layer based on a pattern of the hard mask layer and a pattern of the capped layer.

20. The processing system of claim 14 , wherein the plurality of dual damascene process operations comprise:
forming a barrier layer in each of the plurality of via regions and the plurality of metal line regions;
forming a seed layer

Assignees

• Marvell World Trade Ltd

Inventors

• Chang Runzi
• She Min

Classifications

• H10W20/421

  Skip vias, i.e. vias that do not connect all metallization layers that they pass through · CPC title

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P76/204

  of organic photoresist masks · CPC title

• H10P72/0468

  comprising a chamber adapted to a particular process · CPC title