Method of forming high-voltage silicon-on-insulator device with diode connection to handle layer

Patent metadata

Field	Value
Publication number	US-10522388-B1
Application number	US-201816112466-A
Country	US
Kind code	B1
Filing date	Aug 24, 2018
Priority date	Aug 24, 2018
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

An SOI IC includes a polysilicon/silicon plug extending through the buried insulation layer between a P-type handle layer and a P-type device layer. An N-type well region is formed in the device layer over the polysilicon/silicon plug, and then a high-voltage (HV) device is formed in the well region such that part of its drift region is located over the polysilicon/silicon plug. Doping of the well region, the polysilicon/silicon plug and the handle layer is coordinated to form a P-N junction diode that couples the HV device, by way of the polysilicon/silicon plug, to a ground potential applied to the handle layer, thereby increasing the HV device's breakdown voltage by expanding its depletion region to include the handle layer. The polysilicon/silicon plug grows in holes formed through the insulation layer during the epitaxial silicon growth process used to form the device layer.

First claim

The invention claimed is:

1. A method for fabricating a high voltage (HV) device on a Silicon-On-Insulator (SOI) substrate, the SOI substrate including an insulation layer sandwiched between a handle layer and a top silicon layer, wherein both the handle layer and the top silicon layer have a first doping species type, the method comprising:
defining an opening through the top silicon layer and the insulator layer such that an upper surface portion of the handle layer is exposed in said opening;
forming a device layer by growing epitaxial silicon having said first doping species type such that at least one of polycrystalline silicon and monocrystalline silicon of said epitaxial silicon forms a polysilicon/silicon plug in said opening while said epitaxial silicon forms on an upper surface of the top silicon layer and over the opening, and such that a subsequently grown portion of said epitaxial silicon covering said polysilicon/silicon plug forms said device layer;
forming a well region in the device layer over said polysilicon/silicon plug by implanting a well dopant having a second dopant species type into a corresponding portion of said device layer, and
forming at least a portion of said HV device in said well region such that said HV device is disposed over said polysilicon/silicon plug,
wherein said handle layer, said polysilicon/silicon plug and said well region are configured to form a P-N junction diode coupled between said HV device and a lower surface of said handle layer.

2. The method of claim 1 , wherein forming said well region comprises implanting said well dopant such that a lower boundary of said well region is disposed between an upper surface and a lower surface of said device layer, whereby a P-N interface of said P-N junction diode is disposed in said device layer.

3. The method of claim 1 , wherein forming said well region comprises implanting said well dopant such that said well region extends entirely between an upper surface of said device layer and an upper surface of the insulator layer, whereby a P-N interface of said P-N junction diode is located between an upper end surface of said polysilicon/silicon plug and said lower surface of said handle layer.

4. The method of claim 3 , wherein forming said well region comprises implanting said well dopant such that said portion of said well dopant diffuses entirely through said polysilicon/silicon plug and into a diffusion region of said handle layer, whereby a P-N interface of said P-N junction diode is located between a lower end surface of said polysilicon/silicon plug and said lower surface of said handle layer.

5. The method of claim 1 , further comprising, after defining said opening through the top silicon layer and the insulator layer and before forming said device layer, forming a plug implant in a portion of said handle layer by directing a plug implant dopant of said second doping species type through said opening and said exposed upper surface portion of the handle layer,
wherein forming said well region comprises implanting said well dopant such that said well region extends entirely between an upper surface of said device layer and an upper surface of the insulator layer, and such that a portion of said well dopant diffuses entirely through said polysilicon/silicon plug to said upper surface portion of the handle layer such that a conductive path is formed between said well region and said plug implant, whereby a P-N interface of said P-N junction diode is located at a peripheral boundary of said plug implant inside said handle layer.

6. The method of claim 1 ,
wherein the first doping species type comprises one or more P-type dopants such that said handle layer, said top silicon layer and said device layer comprise P-doped silicon,
wherein said second dopant species type comprises one or more N-type dopants such that said well region comprises N-doped silicon, and
wherein forming said HV device comprises forming an NMOS transistor in said N-type well region.

7. The method of claim 1 ,
wherein the first doping species type comprises one or more P-type dopants such that said handle layer, said top silicon layer and said device layer comprise P-doped silicon,
wherein said second dopant species type comprises one or more N-type dopants such that said well region comprises N-doped silicon,
wherein the method further comprises forming a P-drift region inside said N-type well region, and
wherein forming said HV device comprises forming at least a portion of a PMOS transistor in said P-drift region.

8. The method of claim 1 ,
wherein the first doping species type comprises one or more N-type dopants such that said handle layer, said top silicon layer and said device layer comprise N-doped silicon,
wherein said second dopant species type comprises one or more P-type dopants such that said well region comprises P-doped silicon, and
wherein forming said HV device comprises forming a PMOS transistor in and over said P-doped silicon of said well region.

9. The method of claim 1 , wherein forming said HV device comprises forming a first region and a second region on said upper surface of said device layer such that said first region and said second region are laterally disposed on opposite sides of said polysilicon/silicon plug, and such that said polysilicon/silicon plug is entirely disposed under a drift region extending between said first region and said second region of said HV device.

10. The method of claim 9 , wherein said HV device comprises an LDMOS device.

11. A method for fabricating a high voltage (HV) device on a Silicon-On-Insulator (SOI) substrate, the SOI substrate including an insulation layer sandwiched between a handle layer and a top silicon layer, wherein both the handle layer and the top silicon layer have a first doping species type, the method comprising:
defining an opening through the top silicon layer and the insulator layer such that an upper surface portion of the handle layer is exposed in said opening;
forming a plug implant in a portion of said handle layer by directing a plug implant dopant of a second doping species type through said opening and said exposed upper surface portion of the handle layer;
forming a device layer by growing epitaxial silicon having said first doping species type such that at least one of polycrystalline silicon and monocrystalline silicon of said epitaxial silicon forms a polysilicon/silicon plug in said opening while said epitaxial silicon forms on an upper surface of the top silicon layer and over the opening, and such that a subsequently grown portion of said epitaxial silicon covering said polysilicon/silicon plug forms said device layer;
forming a well region in the device layer over said polysilicon/silicon plug by implanting a dopant having said second dopant species type into a corresponding portion of said device layer such that said well region extends entirely between an upper surface of said device layer and an upper surface of the insulator layer, and a portion of said well dopant diffuses entirely through said polysilicon/silicon plug to said plug implant, and
forming at least a portion of said HV device in said well region.

Assignees

• Tower Semiconductor Ltd

Inventors

• Arad Einat Ophir
• Levin Sharon
• Parag Allon
• Lipp Eran
• Avrahamov Yosef

Classifications

• H10W15/01

  Manufacture or treatment · CPC title

• H10W15/00 Primary

  Highly-doped buried regions of integrated devices · CPC title

• H01L29/0684

  Electricity · mapped topic

• H01L29/861

  Electricity · mapped topic

• H01L21/74 Primary

  Electricity · mapped topic