Processing system with interspersed processors with multi-layer interconnection

Patent metadata

Field	Value
Publication number	US-10521285-B2
Application number	US-201916252904-A
Country	US
Kind code	B2
Filing date	Jan 21, 2019
Priority date	Nov 21, 2012
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.

First claim

What is claimed is:

1. An apparatus, comprising:
a plurality of processors;
a plurality of communication circuits coupled to the plurality of processors in an interspersed arrangement, wherein each one of the plurality of communication circuits is coupled to a plurality of interconnection networks, and wherein a particular one of the plurality of communication circuits is configured to:
receive a message that includes one or more data words via a particular interconnection network of the plurality of interconnection networks; and
forward the message, based on routing information included in the message, to another communication circuit of the plurality of communication circuits using a different one of the plurality of interconnection networks.

2. The apparatus of claim 1 , wherein the particular one of the plurality of communication circuits includes a plurality of layer switch circuits coupled to a plurality of direction switch circuits, wherein a given direction switch circuit of the plurality of direction switch circuits maps to a corresponding interconnection network of the plurality of interconnection networks.

3. The apparatus of claim 2 , wherein a layer switch of the plurality of layer switch circuits that is coupled to the particular one of the plurality of interconnection networks and is configured to relay the message to the given direction switch circuit of the plurality of direction switch circuits that is coupled to a different interconnection network of the plurality of interconnection networks.

4. The apparatus of claim 2 , wherein the particular one of the plurality of communications circuits further includes a memory switch coupled to a memory and two or more processors of the plurality of processors, wherein the memory switch is configured to relay, based on the routing information, the data words of the message to one of the two or more processors.

5. The apparatus of claim 1 , wherein the message includes data, wherein the particular one of the plurality of communication circuits includes a memory circuit, and wherein the particular one of the plurality of communication circuits is further configured to store, based on the routing information, the data in the memory circuit.

6. The apparatus of claim 1 , wherein the particular one of the plurality of communication circuits is further configured to forward the message to the different one of the plurality of communication circuits using configuration information received via a serial bus.

7. A method, comprising:
receiving, by a particular communication circuit of a plurality of communication circuits, a message that includes routing information via a particular interconnection network of a plurality of interconnection networks, wherein each communication circuit of the plurality of communication circuits is coupled to the plurality of interconnection networks, and wherein the plurality of communication circuits is coupled to a plurality of processors in an interspersed fashion;
selecting, by the particular communication circuit, a different one of the plurality of interconnection networks based on the routing information; and
sending, by the particular communication circuit, the message to a different communication circuit of the plurality of communication circuits using a different interconnection network of the plurality of interconnection networks.

8. The method of claim 7 , wherein said receiving of the message by the particular communication circuit, from the particular interconnection network of the interconnection networks includes selectively coupling, based on the routing information, the particular interconnection network of the interconnection networks to a given direction switch circuit of a plurality of direction switch circuits coupled to the particular interconnection network of the plurality of interconnection networks, wherein the plurality of direction switch circuits are included in the particular communication circuit.

9. The method of claim 8 , wherein sending, by the particular communication circuit, the message to the different communication circuit includes relaying the message, from a given layer switch circuit of a plurality of layer switch circuits to the given direction switch circuit of the plurality of direction switch circuits that is coupled to the different one of the plurality of interconnections networks, wherein the plurality of layer switch circuits are included in the particular communication circuit.

10. The method of claim 8 , further comprising, routing the message, based on routing information, to a particular processor of the plurality of processors using a layer switch coupled to a memory switch that is coupled to a memory and to a subset of processors of the plurality of processors.

11. The method of claim 8 , further comprising, storing data included in the message in a memory circuit included in the particular communication circuit of the plurality of communication circuits.

12. The method of claim 7 , wherein sending, by the particular communication circuit, the message to the different communication circuit of the plurality of communication circuits includes forwarding the message to the different one of the plurality of communication circuits using configuration information received via a serial bus.

13. The method of claim 7 , further comprising sending, by the particular communication circuit, the message to the different one of the plurality of communication circuits based upon an amount of message traffic to the different one of the plurality of communication circuits.

14. An apparatus, comprising:
a plurality of layer switch circuits; and
a plurality of direction switch circuits coupled to a of a plurality of interconnection networks, and wherein a particular direction switch circuit of the plurality of direction switch circuits is configured to:
receive a message that includes one or more data words via a particular one of the plurality of interconnection networks coupled to the particular direction switch circuit; and
forward the message, based on routing information included in the message, to a destination by relaying the message using one or more layer switch circuits of the plurality of layer switch circuits to a different one of the plurality of interconnection networks.

15. The apparatus of claim 14 , wherein a given direction switch circuit of the plurality of direction switch circuits is coupled to a given processor of a plurality of processors, and is configured to route the message, based on the routing information, to the given processor of the plurality of processors using a memory switch that is coupled to a subset of processors of the plurality of processors, wherein the memory switch is configured to route the message, based on the routing information, to the given processor.

16. The apparatus of claim 14 , wherein to forward the message, the particular direction switch circuit is further configured to:
receive the message from a first layer switch circuit of the plurality of layer switch circuits; and
relay the message to a second layer switch circuit of the plurality of layer switch circuits, wherein the second layer switch circuit is coupled to the different one of the plurality of interconnection networks.

17. The apparatus of claim 14 , wherein the apparatus further comprises:
an input register circuit configured to store incoming data words included in an incoming message; and
an output register circuit configured to store outgoing data words included in an outgoing message.

18. The apparatus of claim

Assignees

• Coherent Logix Inc

Inventors

• Dobbs Carl S
• Trocino Michael R
• Solka Michael B

Classifications

• G06F15/8038

  Associative processors · CPC title

• G06F9/44505

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• G06F13/1673

  using buffers · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F9/546 Primary

  Message passing systems or structures, e.g. queues · CPC title