Physical partitioning of computing resources for server virtualization

Patent metadata

Field	Value
Publication number	US-10521273-B2
Application number	US-201715617190-A
Country	US
Kind code	B2
Filing date	Jun 8, 2017
Priority date	Jun 8, 2017
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

A baseboard management controller (BMC) can physically partition the computing resources of a physical host into different resource groups for concurrently running a different operating system per resource group. The BMC can allocate a first processor of the host to a first resource group and a second processor of the host to a second resource group. The BMC can separate the memory of the host into a first memory range for the first processor and a second memory range for the second processor, and the BMC can limit access to the first memory range to the first processor and limit access to the second memory range to the second processor. The BMC can also distribute physical or virtual peripheral devices of the host between the first processor and the second processor.

First claim

The invention claimed is:

1. A computer-implemented method, comprising:
determining, by a baseboard management controller of a physical host, that the physical host includes at least a first processor and a second processor;
configuring, by the baseboard management controller, one or more first memory controllers to provide access of the first processor to a first range of memory of the physical host, the first processor denied access to other ranges of memory of the physical host including a second range of memory of the physical host by one or more second memory controllers;
limiting access of the second processor to the second range of memory of the physical host;
loading a first operating system within the first range of memory and a second operating system in the second range of memory;
executing, by the first processor, the first operating system within the first range of memory; and
executing, by the second processor, the second operating system within the second range of memory.

2. The computer-implemented method of claim 1 , wherein the one or more first memory controllers are configured to control the first range of memory.

3. The computer-implemented method of claim 2 , further comprising:
configuring the one or more second memory controllers to deny the access of the first processor to the other ranges of memory of the physical host, the one or more second memory controllers not having control over the first range of memory.

4. The computer-implemented method of claim 1 , further comprising:
generating a memory map that maps the first range of memory to a first set of dual inline memory modules (DIMMs) of the physical host and that excludes mappings to other DIMMs of the physical host.

5. The computer-implemented method of claim 1 , further comprising:
disabling cache coherency between the first range of memory and the second range of memory.

6. The computer-implemented method of claim 1 , further comprising:
receiving at least a first boot image including first instructions for loading the first operating system and a second boot image including second instructions for loading the second operating system;
loading the first boot image into the first range of memory and the second boot image into the second range of memory;
executing, by the first processor, the first instructions for loading the first operating system; and
executing, by the second processor, the second instructions for loading the second operating system.

7. The computer-implemented method of claim 1 , further comprising:
providing, by the baseboard management controller, access to the first processor to an input/output (I/O) port of the physical host by exposing the I/O port to the first processor.

8. The computer-implemented method of claim 1 , further comprising:
denying, by the baseboard management controller, access to the first processor to an I/O port of the physical host by hiding the I/O port from the first processor.

9. The computer-implemented method of claim 1 , further comprising:
mapping, by the baseboard management controller, memory of a peripheral device to the first range of memory to provide access to the first processor to the peripheral device.

10. The computer-implemented method of claim 1 , further comprising:
denying, by the baseboard management controller, access to a peripheral device connected to the physical host by excluding a mapping of memory of the peripheral device to the first range of memory.

11. The computer-implemented method of claim 1 , further comprising:
sending, by the first processor, an I/O request to a peripheral device connected to the physical host; and
receiving, by the first processor, an I/O response from the peripheral device.

12. The computer-implemented method of claim 1 , further comprising:
sending, by the first processor, an I/O request to a peripheral device connected to the physical host; and
ignoring, by the peripheral device, the I/O request.

13. A server comprising:
a processing subsystem;
a memory subsystem; and
a baseband management controller including:
a baseband processor; and
baseboard memory including instructions that, upon execution by the baseband processor, cause the server to:
determine the processing subsystem includes one or more first processors and one or more second processors;
configure one or more first memory controllers to provide access of the one or more first processors to a first range of the memory subsystem, the one or more first processors denied access to other ranges of the memory subsystem including a second range of the memory subsystem by one or more second memory controllers;
limit access of the one or more second processors to the second range of the memory subsystem;
load a first operating system within the first range of the memory subsystem and a second operating system within the second range of the memory subsystem; and
cause the one or more first processors to execute the first operating system within the first range of the memory subsystem and the one or more second processors to execute the second operating system within the second range of the memory subsystem.

14. The server of claim 13 ,
wherein,
the one or more first processors include a first central processing unit (CPU), and
the one or more second processors include a second CPU.

15. The server of claim 13 ,
wherein,
the one or more first processors include a first core of a multi-core processor, and
the one or more second processors include a second core of the multi-core processor.

16. The server of claim 13 ,
wherein,
the one or more first processors include a first core of a first multi-core processor, and
the one or more second processors include a second core of a second multi-core processor.

17. A non-transitory computer-readable medium having instructions that, upon execution by a processor of baseboard management controller (BMC) of a physical host, cause the BMC to:
allocate one or more first processors of the physical host to a first resource group;
allocate one or more second processors of the physical host to a second resource group;
configure one or more first memory controllers to provide access of the one or more first processors to a first range of memory of the physical host, the one or more processors denied access to other ranges of memory of the physical host including a second range of memory of the physical host by one or more second memory controllers;
limit access of the one or more second processors to the second range of memory of the physical host;
load a first operating system within the first range of memory; load a second operating system within the second range of memory;
cause the one or more first processors to execute the first operating system within the first range of memory; and
cause the one or more second processors to execute the second operating system within the second range of memory.

18. The non-transitory computer-readable medium of claim 17 , wherein the instructions upon execution further cause the BMC to:
virtualize a physical memory controller of the physical host to create a first virtual memory controller and a second virtual memory controller;
allocate the first virtual memory controller to the first resource group; and
allocate the second virtual memory controller to the second resource group.

19. The non-transitory computer-readable medium of claim 17 , wherein the physical host is a single-socket server, and wherein the instructions upon execution furthe

Assignees

• Cisco Tech Inc

Inventors

• Mullender Sape
• Barach David Richard
• Mckie Jim
• Bosch Peter

Classifications

• G06F9/5061

  Partitioning or combining of resources · CPC title

• G06F2009/45583

  Memory management, e.g. access or allocation · CPC title

• G06F9/4406 Primary

  Loading of operating system · CPC title

• G06F3/0664

  at device level, e.g. emulation of a storage device or system · CPC title

• G06F9/45558

  Hypervisor-specific management and integration aspects · CPC title