Method of controlling virtualization software on a multicore processor

US9639486B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9639486-B2
Application numberUS-201414528529-A
CountryUS
Kind codeB2
Filing dateOct 30, 2014
Priority dateOct 31, 2013
Publication dateMay 2, 2017
Grant dateMay 2, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A computer, having: a first OS to which a first processor core group is allocated; and a virtualization module to which a second processor core group is allocated, wherein a virtualization module registers interrupt handler processing for resetting the second processor core group, wherein a first OS has: a monitoring module for monitoring the virtualization module; and an interrupt control module for obtaining identifiers of the second processor core group at a time of booting of the virtualization module, and, when the monitoring module determines to reboot the virtualization module, issuing resetting interrupt to the processor cores of the second processor core group that are associated with the kept identifiers, wherein the second processor core group receives the resetting interrupt and executes the interrupt handler processing to reset its own processor cores, wherein the interrupt control module issues startup interrupt to the second processor core group.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of controlling a computer, the computer comprising: a multicore processor having a function of hardware-assisted virtualization; a memory; a first processor core group of processor cores of the multicore processor where the hardware-assisted virtualization is disabled; a second processor core group of processor cores of the multicore processor where the hardware-assisted virtualization is enabled; a first memory group comprising a partial area of the memory; and a second memory group comprising a remaining area of the memory, the method comprising: a first step of allocating the first processor core group and the first memory group to a first OS, and booting the first OS; a second step of allocating the second processor core group and the second memory group to a virtualization module, which runs a virtual machine, and booting the virtualization module; a third step of allocating, by the virtualization module, a given area of the memory and given processor cores of the second processor core group to the virtual machine, and booting a second OS; a fourth step of registering, by the virtualization module, interrupt handlers for resetting the second processor core group; a fifth step of obtaining and keeping, by the first OS, identifiers of the processor cores that belong to the second processor core group when the virtualization module is booted; a sixth step of monitoring, by the first OS, an operation state of the virtualization module and determining whether or not the virtualization module is to be rebooted, based on given conditions; a seventh step of issuing, by the first OS, when the virtualization module is to be rebooted, resetting interrupt to the processor cores belonging to the second processor core group that are associated with the kept identifiers; an eighth step of receiving, by the second processor core group that is allocated to the virtualization module, the resetting interrupt and executing the interrupt handlers to reset the processor cores of the second processor core group; and a ninth step of issuing, by the first OS, startup interrupt to the second processor core group. 2. The method of controlling a computer according to claim 1 , wherein the fourth step comprises registering, by the virtualization module, self-reset processing of the processor cores of the second processor core group in interrupt handlers that are associated with the respective processor cores of the second processor core group, as the interrupt handlers for resetting the second processor core group, and wherein the eighth step comprises receiving, by the second processor core group, the resetting interrupt, and calling up the registered interrupt handlers to execute the self-reset processing for each of the processor cores of the second processor core group independently of one another. 3. The method of controlling a computer according to claim 1 , wherein the sixth step comprises: monitoring, by the first OS, the operation state of the virtualization module, and determining whether or not an abnormality has occurred; and determining, by the first OS, to reboot the virtualization module when it is determined that an abnormality has occurred. 4. The method of controlling a computer according to claim 1 , wherein the seventh step comprises issuing non-maskable interrupt (NMI) as the resetting interrupt. 5. The method of controlling a computer according to claim 2 , wherein, in the self-reset processing, the interrupt handlers issue processor core initializing interrupt to the processor cores of the second processor core group. 6. The method of controlling a computer according to claim 2 , wherein the ninth step comprises issuing, after a given period of time elapses since the resetting interrupt is issued in the seventh step to the processor cores belonging to the second processor core group, by an interrupt control module, Startup Inter Processor Interrupt (SIPI) to the second processor core group. 7. The method of controlling a computer according to claim 4 , wherein the third step comprises setting so that, when the NMI is received in a state where the second OS is run on the virtual machine, processing of the NMI is shifted to the virtualization module instead of transferring the NMI to the virtual machine, wherein the fourth step comprises registering, by the virtualization module, in the interrupt handlers of the respective processor cores in the second processor core group, a command to disable the hardware-assisted virtualization and a command to issue processor core initializing interrupt to the processor cores of the second processor core group, and wherein in addition to issuing, to the virtualization module, by the first OS, the startup interrupt to the second processor core group, the ninth step comprises: receiving, by the second processor core group, the startup interrupt and issuing a command to enable the hardware-assisted virtualization to the processor cores of the second processor core group; and rebooting the virtualization module by the second processor core group. 8. A computer, comprising: a multicore processor having a function of hardware-assisted virtualization; a memory; a first processor core group of processor cores of the multicore processor where the hardware-assisted virtualization is disabled; a second processor core group of processor cores of the multicore processor where the hardware-assisted virtualization is enabled; a first memory group comprising a partial area of the memory; a second memory group comprising a remaining area of the memory; a first OS to which the first processor core group and the first memory group are allocated; and a virtualization module to which the second processor core group and the second memory group are allocated, for running a virtual machine, wherein the virtualization module registers interrupt handler processing for resetting the second processor core group, allocates a given area of the memory and given processor cores of the second processor core group to the virtual machine, and boots a second OS, wherein the first OS comprises: a monitoring module for monitoring an operation state of the virtualization module to determine, based on given conditions, whether or not to reboot the virtualization module; and an interrupt control module for obtaining and keeping identifiers of the respective processor cores that belong to the second processor core group at a time of booting of the virtualization module, and, when the monitoring module determines to reboot the virtualization module, issuing resetting interrupt to the processor cores belonging to the second processor core group that are associated with the kept identifiers, wherein the second processor core group that is allocated to the virtualization module receives the resetting interrupt and executes the interrupt handler processing to reset its own processor cores, and wherein the interrupt control module issues startup interrupt to the second processor core group. 9. The computer according to claim 8 , wherein the virtualization module registers self-reset processing of the processor cores of the second processor core group in interrupt handlers that are associated with the respective processor cores of the second processor core group, as the interrupt handlers for resetting the second processor core group, and wherein the second processor core group receives the resetting interrupt, and calls up the registered interrupt handlers to execute the self-reset processing for each of the processor cores of the second processor core group independently of one another. 10. The computer according to claim 8 , wherein the mo

Assignees

Inventors

Classifications

  • Hypervisor-specific management and integration aspects · CPC title

  • G06F13/24Primary

    using interrupt (G06F13/32 takes precedence) · CPC title

  • Loading of operating system · CPC title

  • Cross-Sectional Technologies · mapped topic

  • Starting, stopping, suspending or resuming virtual machine instances · CPC title

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What does patent US9639486B2 cover?
A computer, having: a first OS to which a first processor core group is allocated; and a virtualization module to which a second processor core group is allocated, wherein a virtualization module registers interrupt handler processing for resetting the second processor core group, wherein a first OS has: a monitoring module for monitoring the virtualization module; and an interrupt control modu…
Who is the assignee on this patent?
Hitachi Ltd
What technology area does this patent fall under?
Primary CPC classification G06F13/24. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 02 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).