Hybrid low power homogenous grapics processing units

Patent metadata

Field	Value
Publication number	US-10521271-B2
Application number	US-201715477026-A
Country	US
Kind code	B2
Filing date	Apr 1, 2017
Priority date	Apr 1, 2017
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

First claim

The invention claimed is:

1. A general purpose graphics processor, comprising:
a plurality of execution units comprising at least a first type of execution unit having a first set of execution resources and a second type of execution unit having a second set of execution resources, different from the first set of execution resources; and
a thread scheduler to:
receive, from a graphics driver, a workload resource requirement data set for a graphics workload to be executed by the general purpose graphics processor;
parse a workload requirement data set;
define a set of work group boundaries within the workload;
assign the workload to one of the first type of execution unit or the second type of execution unit based at least in part on the workload requirement data set, wherein:
the first type of execution unit is a low-performance execution unit;
the second type of execution unit is a high-performance execution unit; and
the first type of execution unit and the second type of execution unit are communicatively coupled to a common memory structure;

save a workload context when execution of the workload reaches a work group boundary in the set of work group boundaries; and
reassign the workload to a different execution unit based at least in part on a physical proximity to resources associated with a related workload.

2. The general purpose graphics processor of claim 1 , wherein:
the first type of execution unit and the second type of execution unit reside on a common processor.

3. The general purpose graphics processor of claim 1 , further comprising logic, wherein:
the first type of execution unit and the second type of execution unit are separate processing structures.

4. The general purpose graphics processor of claim 1 , the processor to:
determine an execution resource requirement from the one or more characteristics of the workload.

5. The general purpose graphics processor of claim 1 , wherein the plurality of execution units are on a single integrated circuit.

6. An electronic device, comprising:
a general purpose graphics processor having a plurality of execution units comprising at least a first type of execution unit having a first set of execution resources and a second type of execution unit having a second set of execution resources, different from the first set of execution resources; and
a thread scheduler to:
receive, from a graphics driver, a workload resource requirement data set for a graphics workload to be executed by the general purpose graphics processor;
parse a workload requirement data set;
define a set of work group boundaries within the workload;
assign the workload to one of the first type of execution unit or the second type of execution unit based at least in part on the workload requirement data set, wherein:
the first type of execution unit is a low-performance execution unit;
the second type of execution unit is a high-performance execution unit; and
the first type of execution unit and the second type of execution unit are communicatively coupled to a common memory structure;

save a workload context when execution of the workload reaches a work group boundary in the set of work group boundaries; and
reassign the workload to a different execution unit based at least in part on a physical proximity to resources associated with a related workload.

7. The electronic device of claim 6 , wherein:
the first type of execution unit and the second type of execution unit reside on a common processor.

8. The electronic device of claim 6 , further comprising logic, wherein:
the first type of execution unit and the second type of execution unit are separate processing structures.

9. The electronic device of claim 6 , the processor to:
determine an execution resource requirement from the one or more characteristics of the workload.

10. The electronic device of claim 6 , wherein the plurality of execution units are on a single integrated circuit.

Assignees

• Intel Corp

Inventors

• Appu Abhishek R
• Koker Altug
• Vembu Balaji
• Ray Joydeep
• Sinha Kamal
• Surti Prasoonkumar
• Veernapu Kiran C
• Maiyuran Subramaniam
• Jahagirdar Sanjeev S
• Asperheim Eric J
• Lueh Guei-Yuan
• Puffer David
• Fu Wenyin
• Kaburlasos Nikos
• Borole Bhushan M
• Mastronarde Josh B
• Hurd Linda L
• Schluessler Travis T
• Janczak Tomasz
• Venkatesh Abhishek
• Xiao Kai
• Grajewski Slawomir

Classifications

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T1/60

  Memory management · CPC title

• G06T2200/28

  involving image processing hardware · CPC title

• G06F9/4893

  taking into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• G06F9/5016 Primary

  the resource being the memory · CPC title