Fast switching and ultra-low power compact varactor driver
US-2024356509-A1 · Oct 24, 2024 · US
US10520554B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10520554-B2 |
| Application number | US-201916269331-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 6, 2019 |
| Priority date | Dec 29, 2016 |
| Publication date | Dec 31, 2019 |
| Grant date | Dec 31, 2019 |
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A circuit includes an amplifier having a first power terminal configured to be coupled to a supply voltage and a second power terminal configured to be coupled to a reference potential. The circuit further includes a first impedance element coupled between a first input terminal of the amplifier and a first output terminal of the amplifier. The circuit additionally includes a second impedance element coupled between the first input terminal and the reference potential. The amplifier is configured to output a first voltage at a second output terminal of the amplifier in response to the supply voltage being greater than an output voltage at the first output terminal of the amplifier. The amplifier is further configured to output a second voltage at the second output terminal of the amplifier in response to the supply voltage being less than the output voltage at the first output terminal of the amplifier.
Opening claim text (preview).
What is claimed is: 1. A circuit, comprising: an operational amplifier comprising a non-inverting input terminal, an inverting input terminal, a first output terminal, and a second output terminal, the operational amplifier further comprising a first power terminal configured to be coupled to a supply voltage and a second power terminal configured to be coupled to a reference potential, the non-inverting input terminal being configured to receive a bandgap reference voltage; a first impedance element coupled between the first output terminal of the operational amplifier and the inverting input terminal of the operational amplifier; a second impedance element coupled between the inverting input terminal of the operational amplifier and the reference potential; and a transistor comprising a gate terminal coupled to the second output terminal of the operational amplifier, the transistor further comprising a source terminal configured to be coupled to the supply voltage, and a drain terminal configured to provide a voltage to an input terminal of a digital buffer, wherein an operation of the transistor is controlled by a difference between the supply voltage and an output voltage at the second output terminal of the operational amplifier. 2. The circuit of claim 1 , wherein a voltage at the second output terminal of the operational amplifier is substantially equal to the supply voltage when the supply voltage is greater than the voltage at the first output terminal of the operational amplifier. 3. The circuit of claim 1 , wherein the voltage at the second output terminal of the operational amplifier is substantially equal to the reference potential when the supply voltage is less than the voltage at the first output terminal of the operational amplifier. 4. The circuit of claim 1 , wherein the voltage at the first output terminal of the operational amplifier comprises a minimum voltage at which an electronic device may safely operate according to a specification of the electronic device. 5. The circuit of claim 1 , wherein a voltage at the non-inverting input terminal of the operational amplifier is equal to a voltage at the inverting input terminal of the operational amplifier. 6. The circuit of claim 1 , further comprising a third impedance element coupled between the drain terminal of the transistor and the reference potential. 7. The circuit of claim 1 , wherein the transistor comprises a p-type metal-oxide-semiconductor transistor. 8. A circuit, comprising: a first constant current source comprising a first terminal configured to be coupled to a reference voltage; a first transistor having a first conductivity type and comprising a first source/drain terminal coupled to a second terminal of the first constant current source; a second transistor having the first conductivity type and comprising a second source/drain terminal coupled to the second terminal of the first constant current source; a third transistor having a second conductivity type different from the first conductivity type, the third transistor comprising a third drain/source terminal coupled to a first drain/source terminal of the first transistor and to a gate terminal of the third transistor, the third transistor further comprising a third source/drain terminal configured to be coupled to a supply voltage; a fourth transistor having the second conductivity type and comprising a fourth drain/source terminal coupled to a second drain/source terminal of the second transistor, the fourth transistor further comprising a gate terminal coupled to the gate terminal of the third transistor, the fourth transistor further comprising a fourth source/drain terminal configured to be coupled to the supply voltage; a fifth transistor having the second conductivity type and comprising a gate terminal coupled to the fourth drain/source terminal of the fourth transistor, the fifth transistor further comprising a fifth source/drain terminal configured to be coupled to the supply voltage; and a sixth transistor having the second conductivity type and comprising a gate terminal coupled to the gate terminal of the fifth transistor, the sixth transistor further comprising a sixth source/drain terminal configured to be coupled to the supply voltage, the sixth transistor further comprising a sixth drain/source terminal configured to be coupled to an input terminal of a buffer. 9. The circuit of claim 8 , further comprising a second constant current source coupled between a fifth drain/source terminal of the fifth transistor and the reference voltage. 10. The circuit of claim 8 , further comprising: a first impedance element coupled between a fifth drain/source terminal of the fifth transistor and a gate terminal of the first transistor; and a second impedance element coupled between the gate terminal of the first transistor and the reference voltage. 11. The circuit of claim 8 , further comprising a third impedance element coupled between the sixth drain/source terminal of the sixth transistor and the reference voltage. 12. The circuit of claim 8 , wherein a gate terminal of the second transistor is configured to receive a bandgap reference voltage. 13. The circuit of claim 12 , wherein the bandgap reference voltage is about 1.2 V. 14. The circuit of claim 8 , wherein the first conductivity type and the second conductivity type comprise an n-type conductivity and a p-type conductivity, respectively. 15. The circuit of claim 8 , wherein the buffer is configured to generate a control signal in response to a voltage at the sixth drain/source terminal of the sixth transistor. 16. The circuit of claim 15 , wherein the control signal is indicative of whether the fifth transistor is operating in a first mode or in a second mode. 17. The circuit of claim 16 , wherein the first mode and the second mode comprise a linear mode and a saturation mode of the fifth transistor, respectively. 18. The circuit of claim 8 , wherein a current flowing between a fifth drain/source terminal of the fifth transistor and the gate terminal of the first transistor is constant and independent of the supply voltage. 19. The circuit of claim 8 , wherein a voltage at a gate terminal of the first transistor is equal to a voltage at a gate terminal of the second transistor. 20. The circuit of claim 8 , further comprising a battery and an electronic device, wherein the battery provides the supply voltage to the electronic device and the fifth transistor.
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