Process for creating dense pillars using multiple exposures for MRAM fabrication

Patent metadata

Field	Value
Publication number	US-10516094-B2
Application number	US-201715857382-A
Country	US
Kind code	B2
Filing date	Dec 28, 2017
Priority date	Dec 28, 2017
Publication date	Dec 24, 2019
Grant date	Dec 24, 2019

Abstract

A method for a photolithographic fabricating process to define pillars having small pitch and pillar size. The method includes coating a hard mask layer of a wafer with a photoresist. The wafer is exposed with a first line pattern comprising a plurality of parallel lines in a first direction. The wafer is then exposed with a second line pattern comprising a plurality of parallel lines in a second direction orthogonal to the first direction. The wafer is then developed to remove areas of the photoresist that were exposed by the first line pattern and the second line pattern resulting in a plurality of pillars.

First claim

What is claimed is:

1. A method for a photolithographic fabricating process for producing a pillar array, the method, comprising:
coating a hard mask layer of a wafer with a photoresist;
exposing the wafer with a first line pattern comprising a plurality of parallel lines in a first direction;
exposing the wafer with a second line pattern comprising a plurality of parallel lines in a second direction orthogonal to the first direction; and
developing the wafer to remove areas of the photoresist that were exposed by the first line pattern and the second line pattern resulting in a plurality of circular solid cylindrical pillars of the pillar array.

2. The method of claim 1 further comprising exposing the wafer with a third line pattern comprising a plurality of parallel lines to reduce a pitch width of the plurality pillars.

3. The method of claim 1 further comprising using a reactive ion etch (RIE) process to transfer the plurality of pillars pattern to the hard mask layer resulting in a patterned hard mask layer.

4. The method of claim 3 further comprising transferring dimensions of the patterned hard mask layer to a film stack below the patterned hard mask layer using an MRAM fabrication process.

5. The method of claim 1 , wherein the hard mask layer is fabricated to be compatible with an electron beam process.

6. The method of claim 1 , wherein the wafer is developed with a positive developer.

7. The method of claim 1 , wherein the first line pattern is of a different pitch than the second line pattern.

8. The method of claim 1 , wherein the first line pattern is of a different size than the second line pattern.

9. A method for reducing pillar pitch width of a wafer fabrication process, the method comprising:
coating a hard mask layer of a wafer with a photoresist;
exposing the wafer with a first line pattern comprising a plurality of parallel lines in a first direction;
exposing the wafer with a second line pattern comprising a plurality of parallel lines in a second direction orthogonal to the first direction;
developing the wafer to remove areas of the photoresist that were exposed by the first line pattern and the second line pattern resulting in a plurality of circular solid cylindrical pillars.

10. The method of claim 9 further comprising exposing the wafer with a third line pattern comprising a plurality of parallel lines to reduce a pitch width of the plurality pillars.

11. The method of claim 9 further comprising using a reactive ion etch (RIE) process to transfer the plurality of pillars pattern to the hard mask layer resulting in a patterned hard mask layer.

12. The method of claim 11 further comprising transferring dimensions of the patterned hard mask layer to a film stack below the patterned hard mask layer using an MRAM fabrication process.

13. The method of claim 9 , wherein the hard mask layer is fabricated to be compatible with an electron beam process.

14. The method of claim 9 , wherein the wafer is developed with a positive developer.

15. The method of claim 9 , wherein the first line pattern is of a different pitch than the second line pattern.

16. The method of claim 9 , wherein the first line pattern is of a different size than the second line pattern.

17. A method for manufacturing an MRAM device, the method comprising:
coating a hard mask layer of a wafer with a photoresist;
exposing the wafer with a first line pattern comprising a plurality of parallel lines in a first direction;
exposing the wafer with a second line pattern comprising a plurality of parallel lines parallel to the first line pattern and offset and interleaved with the first line pattern;
exposing the wafer with at least one additional line pattern comprising a plurality of parallel lines in a second direction orthogonal to the first direction;
developing the wafer to remove areas of the photoresist that were exposed by the first line pattern, the second line pattern and the at least one additional line pattern resulting in a plurality circular solid cylindrical of pillars.

18. The method of claim 17 further comprising using a reactive ion etch (RIE) process to transfer the plurality of pillars pattern to the hard mask layer resulting in a patterned hard mask layer.

19. The method of claim 18 further comprising transferring dimensions of the patterned hard mask layer to a film stack below the patterned hard mask layer using an MRAM fabrication process.

20. The method of claim 17 , wherein the wafer is developed with a positive developer.

Assignees

• Spin Memory Inc

Inventors

• Shrivastava Prachi
• Pinarbasi Mustafa
• Boone Thomas

Classifications

• H10P76/2041 Primary

  Photolithographic processes · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H01L43/12

  Electricity · mapped topic

• H01L43/02 Primary

  Electricity · mapped topic

• H01L21/3065

  Electricity · mapped topic