Method for forming dual-deck channel hole structure of three-dimensional memory device

Patent metadata

Field	Value
Publication number	US-10515975-B1
Application number	US-201816046887-A
Country	US
Kind code	B1
Filing date	Jul 26, 2018
Priority date	Jun 8, 2018
Publication date	Dec 24, 2019
Grant date	Dec 24, 2019

Abstract

A method for forming a channel hole structure of a 3D memory device is disclosed. The method includes: forming a first alternating dielectric stack and a first insulating layer on a substrate; forming a first channel structure in a first channel hole penetrating the first insulating layer and the first alternating dielectric stack; forming a sacrificial inter-deck plug in the first insulating layer; forming a second alternating dielectric stack on the sacrificial inter-deck plug; forming a second channel hole penetrating the second alternating dielectric stack and expose a portion of the sacrificial inter-deck plug; removing the sacrificial inter-deck plug to form a cavity; and forming an inter-deck channel plug in the cavity and a second channel structure in the second channel hole, the inter-deck channel plug contacts the first channel structure and the second channel structure.

First claim

What is claimed is:

1. A method for forming a channel hole structure in a three-dimensional (3D) memory device, comprising:
forming a first alternating dielectric stack on a substrate;
forming a first insulating layer on the first alternating dielectric stack;
forming a first channel hole penetrating the first insulating layer and the first alternating dielectric stack;
forming a first channel structure in the first channel hole;
forming a sacrificial inter-deck plug in the first insulating layer, wherein a projection of the sacrificial inter-deck plug in a lateral plane covers a projection of the first channel hole in the lateral plane;
forming a second alternating dielectric stack disposed on the sacrificial inter-deck plug;
forming a second channel hole penetrating the second alternating dielectric stack and expose a portion of the sacrificial inter-deck plug;
removing the sacrificial inter-deck plug to form a cavity; and
forming an inter-deck channel plug in the cavity and a second channel structure in the second channel hole, wherein the inter-deck channel plug contacts the first channel structure and the second channel structure.

2. The method of claim 1 , wherein at least one of forming the first alternating dielectric stack and forming the second alternating dielectric stack comprises:
forming at least 32 dielectric layer pairs stacked in a vertical direction, wherein each dielectric layer pair includes a first dielectric layer and a second dielectric layer that is different from the first dielectric layer.

3. The method of claim 1 , wherein at least one of forming the first alternating dielectric stack and forming the second alternating dielectric stack comprises:
forming at least 32 dielectric layer pairs stacked in a vertical direction, wherein each dielectric layer pair includes a silicon oxide layer and a silicon nitride layer.

4. The method of claim 1 , further comprising:
forming an oxide layer on the first alternating dielectric stack as the first insulating layer; and
forming a nitride layer on the oxide layer as a first mask layer.

5. The method of claim 1 , further comprising:
before forming the first channel structure, forming an epitaxial layer on a surface of the substrate that is exposed by the first channel hole.

6. The method of claim 5 , wherein forming the first channel structure comprises:
forming a first functional layer on a sidewall of the first channel hole;
forming a first channel layer covering a sidewall of the functional layer, the first channel layer being in contact with the epitaxial layer; and
forming a first filling structure to cover a sidewall of the first channel layer and filling the first channel hole.

7. The method of claim 6 , wherein forming the first functional layer comprises:
forming a first barrier layer on the sidewall of the first channel hole for blocking an outflow of electronic charges;
forming a first storage layer on a surface of the first barrier layer for storing electronic charges during operation of the 3D memory device; and
forming a first tunneling layer on a surface of the first storage layer for tunneling electronic charges.

8. The method of claim 6 , wherein forming the sacrificial inter-deck plug comprises:
forming a first recess in the first insulating layer, wherein a projection of the first recess in the lateral plane covers a projection of the first channel hole in the lateral plane;
forming an oxide and nitride etch stopper layer in the first recess, the oxide and nitride etch stopper layer be in contact with the first channel layer; and
removing a portion of the oxide and nitride etch stopper layer that is outside of the recess to form the sacrificial inter-deck plug, and to planarize a top surface of the sacrificial inter-deck plug.

9. The method of claim 6 , wherein forming the sacrificial inter-deck plug comprises:
depositing a material including tungsten, tungsten silicide, or tungsten nitride to form the oxide and nitride etch stopper layer.

10. The method of claim 6 , before removing the sacrificial inter-deck plug, further comprising:
forming a second functional layer on a sidewall of the second channel hole and on a surface of the sacrificial inter-deck plug exposed by the second channel hole; and
removing a portion of the second functional layer that is on a surface of the sacrificial inter-deck plug.

11. The method of claim 10 , wherein forming the second functional layer comprises:
forming a second barrier layer on the sidewall of the second channel hole for blocking an outflow of the electronic charges;
forming a second storage layer on a surface of the second barrier layer for storing electronic charges during operation of the 3D memory device; and
forming a second tunneling layer on a surface of the second storage layer for tunneling electronic charges.

12. The method of claim 10 , wherein forming the inter-deck channel plug comprises:
forming the inter-deck channel plug in the cavity by a deposition process, wherein the inter-deck channel plug contacts the first channel layer.

13. The method of claim 12 , wherein forming the second channel structure in the first channel hole comprises:
forming the second channel layer on a surface of the second functional layer by a deposition process, wherein the second channel structure contacts the inter-deck channel plug.

14. The method of claim 10 , wherein forming the inter-deck channel plug in the cavity and the second channel structure in the first channel hole comprises:
forming the inter-deck channel plug and the second channel structure in a single deposition process.

15. The method of claim 14 , wherein forming the second channel structure further comprises:
forming a second filling structure to cover a sidewall of the second channel layer and filling the second channel hole.

16. The method of claim 15 , further comprising:
removing a portion of the second filling structure a second recess in the second channel hole; and
forming a top channel plug in the second recess, the top channel plug being in contact with the second channel layer.

17. The method of claim 10 , wherein forming the inter-deck channel plug comprises:
forming the inter-deck channel plug having a thickness less than 60 nm.

18. The method of claim 1 , wherein removing the sacrificial inter-deck plug comprises:
performing a selective wet etching process to etch the sacrificial inter-deck plug through the second channel hole.

19. The method of claim 1 , further comprising:
replacing the second dielectric layers in the first alternating dielectric stack and the second alternating dielectric stack with conductor layers.

20. The method of claim 19 , further comprising:
reducing a thickness of the inter-deck channel plug during replacing the second dielectric layers in the first alternating dielectric stack and the second alternating dielectric stack with conductor layers.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Tao Qian
• Hu Yushi
• Lu Zhenyu
• Xiao li hong
• Chen Jun
• Dai Xiaowang
• Lyu Jin
• Zhu Jifeng
• Dong Jin Wen
• Yao Lan

Classifications

• H10P50/667

  by liquid etching only · CPC title

• H10W20/4451

  Semiconductor materials, e.g. polysilicon · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L27/11582

  Electricity · mapped topic

• H01L21/32134

  Electricity · mapped topic