Sample- and-hold circuit and display device

Patent metadata

Field	Value
Publication number	US-10515709-B2
Application number	US-201615779265-A
Country	US
Kind code	B2
Filing date	Oct 31, 2016
Priority date	Dec 16, 2015
Publication date	Dec 24, 2019
Grant date	Dec 24, 2019

Abstract

A sample-and-hold circuit of the disclosure includes: a differential pair that includes a first MOS transistor and a second MOS transistor, in which respective source terminals of the first MOS transistor and the second MOS transistor are interconnected to a specified node, and an input signal is input to a gate terminal of the first MOS transistor; a capacitor that is coupled to a gate terminal of the second MOS transistor, and samples and holds the input signal; a switch transistor that has a source terminal coupled to the capacitor and the gate terminal of the second MOS transistor, and causes the capacitor to sample and hold the input signal upon application of a predetermined ON voltage; and an ON-voltage control transistor that couples a gate terminal of the switch transistor to the specified node when causing the input signal to be sampled and held.

First claim

The invention claimed is:

1. A sample-and-hold circuit, comprising:
a differential pair that includes a first MOS transistor and a second MOS transistor, wherein respective source terminals of the first MOS transistor and the second MOS transistor being interconnected to a specified node, an input signal being input to a gate terminal of the first MOS transistor;
a capacitor that is coupled to a gate terminal of the second MOS transistor, wherein the capacitor is configured to sample and hold the input signal;
a switch transistor that has a source terminal coupled to the capacitor and the gate terminal of the second MOS transistor, wherein the switch is configured to cause the capacitor to sample and hold the input signal upon application of an ON voltage; and
an ON-voltage control transistor that couples a gate terminal of the switch transistor to the specified node when causing the input signal to be sampled and held.

2. The sample-and-hold circuit according to claim 1 , wherein
the differential pair serves as a negative feedback circuit, where the gate terminal of the first MOS transistor serves as a positive input terminal and the gate terminal of the second MOS transistor serves as a negative input terminal, and when the switch transistor is ON, and
the ON-voltage control transistor couples the gate terminal of the switch transistor to the specified node only in a case where the negative feedback circuit is established.

3. The sample-and-hold circuit according to claim 1 , further comprising an OFF-voltage control transistor that applies an OFF voltage to the gate terminal of the switch transistor, the OFF voltage causing the switch transistor to be turned OFF.

4. The sample-and-hold circuit according to claim 1 , wherein a voltage of the specified node is a sum of a voltage of the input signal and a gate-to-source voltage in the first and the second MOS transistors.

5. The sample-and-hold circuit according to claim 1 , further comprising a power-supply-voltage supply line that supplies a power supply voltage,
wherein a voltage of the specified node when the input signal is sampled and held is a voltage lower than the power supply voltage.

6. A display device including a comparator circuit to which an image signal is input as an input signal, the comparator circuit including a sample-and-hold circuit, wherein the sample-and-hold circuit comprising:
a differential pair that includes a first MOS transistor and a second MOS transistor, wherein respective source terminals of the first MOS transistor and the second MOS transistor being interconnected to a specified node, an input signal being input to a gate terminal of the first MOS transistor;
a capacitor that is coupled to a gate terminal of the second MOS transistor, wherein the capacitor is configured to sample and hold the input signal;
a switch transistor that has a source terminal coupled to the capacitor and the gate terminal of the second MOS transistor, wherein the switch is configured to cause the capacitor to sample and hold the input signal upon application of an ON voltage; and
an ON-voltage control transistor that couples a gate terminal of the switch transistor to the specified node when causing the input signal to be sampled and held.

Assignees

• Sony Corp

Inventors

• CHIBASHI Masaru
• Kikuchi Ken
• Sugiyama Takaaki

Classifications

• G09G2310/0294

  Details of sampling or holding circuits arranged for use in a driver for data electrodes · CPC title

• G11C27/026 Primary

  associated with an amplifier (G11C27/028 takes precedence) · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03F3/45977 Primary

  using switching means, e.g. sample and hold · CPC title

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title