Porous polyurethane polishing pad and process for preparing a semiconductor device by using the same

Patent metadata

Field	Value
Publication number	US-10513007-B2
Application number	US-201815989396-A
Country	US
Kind code	B2
Filing date	May 25, 2018
Priority date	May 29, 2017
Publication date	Dec 24, 2019
Grant date	Dec 24, 2019

Abstract

The embodiments relate to a porous polyurethane polishing pad and a process for preparing a semiconductor device by using the same. The porous polyurethane polishing pad comprises a urethane-based prepolymer and a curing agent, and has a thickness of 1.5 to 2.5 mm, a number of pores whose average diameter is 10 to 60 μm, a specific gravity of 0.7 to 0.9 g/cm3, a surface hardness at 25° C. of 45 to 65 Shore D, a tensile strength of 15 to 25 N/mm2, an elongation of 80 to 250%, an AFM (atomic force microscope) elastic modulus of 30 to 100 MPa measured from a polishing surface in direct contact with an object to be polished to a predetermined depth wherein the predetermined depth is 1 to 10 μm.

First claim

The invention claimed is:

1. A porous polyurethane polishing pad, which comprises
a urethane-based prepolymer;
a solid phase foaming agent in an amount of 0.5 to 10 parts by weight based on 100 parts by weight of the urethane-based prepolymer; and
a curing agent,
wherein the porous polyurethane polishing pad has a thickness of 1.5 to 2.5 mm, a number of pores whose average diameter is 10 to 60 μm, a specific gravity of 0.7 to 0.9 g/cm 3 , a surface hardness at 25° C. of 45 to 65 Shore D, a tensile strength of 15 to 25 N/mm 2 , an elongation of 80 to 250%, an AFM (atomic force microscope) elastic modulus of 30 to 100 MPa measured from a polishing surface in direct contact with an object to be polished to a predetermined depth wherein the predetermined depth is 1 to 10 μm.

2. The porous polyurethane polishing pad of claim 1 , wherein the solid phase foaming agent has an average particle diameter of 10 to 60 μm.

3. The porous polyurethane polishing pad of claim 1 , which has an AFM hardness of the polishing surface of 5 to 60 MPa.

4. The porous polyurethane polishing pad of claim 1 , which has an AFM square root mean roughness of the polishing surface of 40 to 110 nm.

5. The porous polyurethane polishing pad of claim 1 , wherein the pores comprise a number of open pores exposed to the outside, the open pores comprise a first open pore and a second open pore that are adjacent to each other and spaced from each other, and the polishing surface is disposed between the first open pore and the second open pore.

6. The porous polyurethane polishing pad of claim 1 , wherein the area of the polishing surface is 30 to 60% of the total area of the upper surface of the polishing pad.

7. The porous polyurethane polishing pad of claim 5 , wherein the open pores have an average diameter of 10 to 40 μm and an average depth of 8 to 38 μm.

8. A process for preparing a semiconductor device, which comprises providing a porous polyurethane polishing pad; disposing an object to be polished on the polishing pad; and relatively rotating the object to be polished with respect to the polishing pad to polish the object,
wherein the polishing pad comprises a urethane-based prepolymer, a solid phase foaming agent in an amount of 0.5 to 10 parts by weight based on 100 parts by weight of the urethane-based prepolymer, and a curing agent; and
wherein the polishing pad has a thickness of 1.5 to 2.5 mm, a number of pores whose average diameter is 10 to 60 μm, a specific gravity of 0.7 to 0.9 g/cm 3 , a surface hardness at 25° C. of 45 to 65 Shore D, a tensile strength of 15 to 25 N/mm 2 , an elongation of 80 to 250%, an AFM (atomic force microscope) elastic modulus of 30 to 100 MPa measured from a polishing surface in direct contact with the object to be polished to a predetermined depth wherein the predetermined depth is 1 to 10 μm.

9. The process for preparing a semiconductor device of claim 8 , wherein the object to be polished comprises an oxide layer, and the oxide layer is polished by the polishing pad.

Assignees

• Skc Co Ltd

Inventors

• Ahn Jaein
• Seo Jang Won
• Yun Sunghoon
• Moon Su Young
• Kyun Myung-Ok

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P52/402

  of semiconductor materials · CPC title

• B24D3/32

  for porous or cellular structure · CPC title

• B24B37/24 Primary

  characterised by the composition or properties of the pad materials · CPC title