Method for manufacturing the semiconductor structure

Patent metadata

Field	Value
Publication number	US-10178309-B2
Application number	US-201816001367-A
Country	US
Kind code	B2
Filing date	Jun 6, 2018
Priority date	Jan 5, 2016
Publication date	Jan 8, 2019
Grant date	Jan 8, 2019

Abstract

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a gate structure, a first dielectric layer and two air gaps. The gate structure is disposed on the substrate. The gate structure has two opposite side walls. The gate structure comprises a U-shaped structure and a metal gate electrode. The U-shaped structure defines an opening toward upside, and comprises a work function layer. The metal gate electrode is disposed in the opening defined by the U-shaped structure. A level of a top surface of the U-shaped structure is lower than a level of a top surface of the metal gate electrode. The first dielectric layer is disposed on the substrate adjacent to the gate structure. Each of the two air gaps is formed between the first dielectric layer and one of the two opposite side walls of the gate structure.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor structure, comprising:
providing a substrate;
forming a sacrificial gate structure on the substrate, the sacrificial gate structure having two opposite side walls;
forming two sacrificial spacers on the two opposite side walls of the sacrificial gate structure, respectively;
forming a first dielectric layer on the substrate and adjacent to the sacrificial gate structure;
removing the sacrificial gate structure and forming an opening;
forming a gate structure in the opening, the gate structure having two opposite side walls, the gate structure comprising:
a U-shaped structure defining an opening toward upside, the U-shaped structure comprising a work function layer; and
a metal gate electrode formed in the opening defined by the U-shaped structure, wherein a level of a top surface of the U-shaped structure is lower than a level of a top surface of the metal gate electrode; and
removing the sacrificial spacers and forming two air gaps between the first dielectric layer and the two opposite side walls of the gate structure,
wherein each of the air gaps and the U-shaped structure are non-overlapping in a normal direction of a top surface of the substrate.

2. The method according to claim 1 , wherein the air gaps do not extend above the level of the top surface of the U-shaped structure.

3. The method according to claim 1 , wherein forming the gate structure comprises removing portions of materials of the U-shaped structure and the metal gate electrode such that the level of the top surface of the U-shaped structure and the level of the top surface of the metal gate electrode are lower than a level of a top surface of the first dielectric layer.

4. The method according to claim 1 , further comprising:
forming a second dielectric layer on the first dielectric layer such that the second dielectric layer seals the air gaps.

5. The method according to claim 4 , wherein the second dielectric layer is formed of silicon nitride by PECVD.

6. The method according to claim 1 , further comprising:
forming an interfacial dielectric layer on the substrate, wherein the sacrificial gate structure is formed on the interfacial dielectric layer.

7. The method according to claim 1 , wherein the U-shaped structure further comprises a high-k dielectric layer, wherein the work function layer is formed on the high-k dielectric layer.

8. The method according to claim 7 , wherein the U-shaped structure further comprises an etch stop layer, wherein the etch stop layer is formed between the work function layer and the high-k dielectric layer.

9. The method according to claim 8 , wherein the U-shaped structure further comprises a barrier layer, wherein the barrier layer is formed on the work function layer.

10. The method according to claim 1 , further comprising:
forming a fin on the substrate, wherein the sacrificial gate structure is formed on and across the fin.

Assignees

• United Microelectronics Corp

Inventors

• Lin Chien-Ting

Classifications

• H10P50/266

  by vapour etching only · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10W10/021

  of air gaps · CPC title