Method for manufacturing electrode of semiconductor device

Patent metadata

Field	Value
Publication number	US-10510845-B2
Application number	US-201715728160-A
Country	US
Kind code	B2
Filing date	Oct 9, 2017
Priority date	Oct 11, 2016
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

The invention disclosed a method for manufacturing an electrode of a semiconductor device, comprising: forming a first interlayer dielectric layer having a first opening on a first surface of a semiconductor substrate; forming a first resist mask having a second opening on a surface of the first interlayer dielectric layer, wherein the first opening and the second opening are connected to form a first stacked opening; forming a first conductive layer on the first resist mask, wherein the first conductive layer comprises a first portion being located on a surface of the first resist mask and a second portion being located inside the first stacked opening; and removing the first resist mask, wherein the first portion of the first conductive layer is removed together with the first resist mask, and the second portion of the first conductive layer is retained as a first surface electrode.

First claim

The invention claimed is:

1. A method for manufacturing an electrode of a semiconductor device, comprising:
forming a first interlayer dielectric layer having a first opening on a first surface of a semiconductor substrate, wherein said first surface of said semiconductor substrate is partly exposed by the first opening;
forming a first resist mask having a second opening on a surface of said first interlayer dielectric layer by exposure with a light source which provides an ultraviolet light, wherein said first opening and said second opening are connected to form a first stacked opening;
forming a first conductive layer on said first resist mask, wherein said first conductive layer comprises a first portion being located on a surface of said first resist mask and a second portion being located inside said first stacked opening;
removing said first resist mask, wherein said first portion of said first conductive layer is removed together with said first resist mask, and said second portion of said first conductive layer is retained as a first surface electrode;
forming a second interlayer dielectric layer having a third opening on a second surface of said semiconductor substrate, wherein said second surface of said semiconductor substrate is partly exposed by the third opening; and
forming a second conductive layer, wherein portion of said second conductive layer fills said third opening and is retained as a second surface electrode,
wherein said second portion of said first conductive layer fills a portion of said second opening of said first resist mask, and said second surface is opposed to said first surface.

2. The method according to claim 1 , wherein said semiconductor substrate comprises an active region, said step of forming said first interlayer dielectric layer having said first opening on said first surface of said semiconductor substrate comprises:
forming said first interlayer dielectric layer on said first surface of said semiconductor substrate;
forming a second resist mask having said first opening on said surface of said first interlayer dielectric layer;
forming said first interlayer dielectric layer having said first opening by etching said first interlayer dielectric layer through said first opening; and
removing said second resist mask, wherein an exposed portion of said active region of said semiconductor substrate is exposed to the outside through said first opening, and said exposed portion of said active region of said semiconductor substrate is used as a first electrode contact region.

3. The method according to claim 1 , in the process of forming said first resist mask having said second opening, said light source provides an ultraviolet light with constant light intensity and constant wavelength for forming said second opening with steep sidewalls.

4. The method according to claim 1 , wherein said second opening is larger than said first opening and said first opening is fully exposed through said second opening.

5. The method according to claim 1 , wherein said first interlayer dielectric layer has a first thickness, said first resist mask has a second thickness, said first conductive layer has a third thickness, said third thickness is less than a sum of said first thickness and said second thickness, and an upper surface of said second portion of said first conductive layer is lower than an upper surface of said first resist mask.

6. The method according to claim 5 , wherein said third thickness is greater than said first thickness, and said second portion of said first conductive layer fills said first opening, and laterally extends on said first interlayer dielectric layer.

7. The method according to claim 1 , further comprising:
forming a third resist mask having a fourth opening on a surface of said second interlayer dielectric layer, wherein said third opening and said fourth opening are connected to form a second stacked opening,
said second conductive layer comprises a first portion being located on a surface of said third resist mask and a second portion being located inside said second stacked opening; and
removing said third resist mask, wherein said first portion of said second conductive layer is removed together with said third resist mask, and said second portion of said second conductive layer is retained as a second surface electrode.

8. The method according to claim 7 , wherein said semiconductor substrate comprises an active region, the step of forming said second interlayer dielectric layer having said third opening on said second surface of said semiconductor substrate comprises:
forming said second interlayer dielectric layer on said second surface of said semiconductor substrate;
forming a fourth resist mask having said third opening on said surface of said second interlayer dielectric layer;
forming said second interlayer dielectric layer having said third opening by etching said second interlayer dielectric layer through said third opening; and
removing said fourth resist mask, wherein an exposed portion of said active region of said semiconductor substrate is exposed to the outside through said third opening, and the exposed portion of said active region of said semiconductor substrate is used as a second electrode contact region.

9. The method according to claim 7 , wherein said second interlayer dielectric layer and said first interlayer dielectric layer are formed simultaneously.

10. The method according to claim 7 , wherein, in the process of forming said third resist mask having said fourth opening, said light source provides an ultraviolet light with constant light intensity and constant wavelength for forming said fourth opening with steep sidewalls.

11. The method according to claim 7 , wherein said fourth opening is larger than said third opening and said third opening is fully exposed through said fourth opening.

12. The method according to claim 7 , wherein said second interlayer dielectric layer has a first thickness, said third resist mask has a second thickness, said second conductive layer has a third thickness, said third thickness is less than a sum of said first thickness and said second thickness, and an upper surface of said second conductive layer is lower than an upper surface of said third resist mask.

13. The method according to claim 12 , wherein said third thickness is greater than said first thickness, and said second portion of said second conductive layer fills said third opening, and laterally extends on said second interlayer dielectric layer.

14. The method according to claim 1 , wherein said first resist mask is formed from a photoresist mask partially exposed to said light source, said second opening is configured to expand with depth towards said surface of said first interlayer dielectric layer.

15. The method according to claim 7 , wherein said third resist mask is formed from a photoresist mask partially exposed to said light source, said fourth opening is configured to expand with depth towards said surface of said second interlayer dielectric layer.

16. The method according to claim 1 , wherein said first interlayer dielectric layer on said first surface of said semiconductor substrate and said second interlayer dielectric layer on said second surface of said semiconductor substrate are patterned by single-side light separately.

17. A method for manufacturing an electrode of a semiconductor device, comprising:
forming a first interlayer dielectric layer having a first opening on a first surface of a semiconductor substrate;
forming a first resist mask having a second

Assignees

• Silergy Semiconductor Technology Hangzhou Ltd

Inventors

• Yin Dengping
• Wang Shijun
• Yao Fei

Classifications

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/01955

  by using masks · CPC title

• H01L21/283

  Electricity · mapped topic

• H01L21/0272

  Electricity · mapped topic

• H01L2224/03472

  Electricity · mapped topic