Method of manufacturing silicon germanium-on-insulator

Patent metadata

Field	Value
Publication number	US-10510583-B2
Application number	US-201916409038-A
Country	US
Kind code	B2
Filing date	May 10, 2019
Priority date	Jun 1, 2015
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

The disclosed method is suitable for producing a SiGe-on-insulator structure. According to some embodiments of the method, a layer comprising SiGe is deposited on silicon-on-insulator substrate comprising an ultra-thin silicon top layer. In some embodiments, the layer comprising SiGe is deposited by epitaxial deposition. In some embodiments, the SiGe epitaxial layer is high quality since it is produced by engineering the strain relaxation at the Si/buried oxide interface. In some embodiments, the method accomplishes elastic strain relaxation of SiGe grown on a few monolayer thick Si layer that is weakly bonded to the underline oxide.

First claim

What is claimed is:

1. A multilayer structure comprising:
a silicon-on-insulator substrate comprising (i) a single crystal semiconductor handle layer comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor handle layer and the other of which is a back surface of the single crystal semiconductor handle layer, a circumferential edge joining the front and back surfaces of the single crystal semiconductor handle layer, a central plane between and parallel to the front surface and the back surface of the single crystal semiconductor handle layer, a central axis perpendicular to the central plane, and a bulk region between the front and back surfaces of the single crystal semiconductor handle layer, (ii) a dielectric layer in interfacial contact with the front surface of the single crystal semiconductor handle layer, and (ii) a silicon layer in interfacial contact with the dielectric layer, wherein the silicon layer has a thickness between about 0.5 nanometer and about 4 nanometers, as measured along the central axis, and further wherein the silicon layer comprises a hydride-terminated surface;
a first silicon germanium layer in interfacial contact with the hydride-terminated surface of the silicon layer, wherein the first silicon germanium comprises silicon and germanium and has a formula of Si x Ge 1−x , wherein x is between about 0.2 and about 0.8, molar ratio; and
a second silicon germanium layer in interfacial contact with the first silicon germanium layer, wherein the second silicon germanium layer comprises silicon and germanium and has a formula Si y Ge 1−y , wherein y is between about 0.3 and about 0.9, molar ratio.

2. The multilayer structure of claim 1 wherein single crystal semiconductor handle has a resistivity between about 3000 Ohm-cm and about 10,000 Ohm-cm.

3. The multilayer structure of claim 1 wherein the silicon layer comprising the hydride-terminated surface has a thickness between about 0.5 nanometer and about 2 nanometers, as measured along the central axis.

4. The multilayer structure of claim 1 wherein the silicon layer comprising the hydride-terminated surface has a thickness between about 1 nanometer and about 2 nanometers, as measured along the central axis.

5. The multilayer structure of claim 1 wherein the first silicon germanium layer has a thickness between about 0.5 nanometer and about 8 nanometers, as measured along the central axis.

6. The multilayer structure of claim 1 wherein the first silicon germanium layer has a thickness between about 1 nanometer and about 4 nanometers, as measured along the central axis.

7. The multilayer structure of claim 1 wherein the first silicon germanium layer comprises silicon and germanium and has a formula of Si x Ge 1−x , wherein x is between about 0.2 and about 0.4, molar ratio.

8. The multilayer structure of claim 1 wherein the second silicon germanium layer has a thickness between about 2 nanometers and about 5000 nanometers, as measured along the central axis.

9. The multilayer structure of claim 1 wherein the second silicon germanium layer has a thickness between about 2 nanometers and about 500 nanometers, as measured along the central axis.

10. The multilayer structure of claim 1 wherein the second silicon germanium layer has a thickness between about 2 nanometers and about 100 nanometers, as measured along the central axis.

11. The multilayer structure of claim 1 wherein the second silicon germanium layer has a thickness between about 4 nanometers and about 40 nanometers, as measured along the central axis.

12. The multilayer structure of claim 1 wherein the second silicon germanium layer has a threading dislocation density of less than 1×10 6 /cm 2 .

13. The multilayer structure of claim 1 wherein the second silicon germanium layer has surface roughness using RMS (root mean square) of less than 5 angstroms.

14. The multilayer structure of claim 1 wherein the silicon layer comprising the hydride-terminated surface further comprises a surfactant atom selected from the group consisting of arsenic, antimony, tellurium, and any combination thereof.

15. The multilayer structure of claim 1 further comprising a passivation layer comprising silicon in interfacial contact with the second silicon germanium layer.

16. The multilayer structure of claim 1 further comprising boron atoms at the interface between the silicon layer in interfacial and the dielectric layer.

17. The multilayer structure of claim 1 further comprising boron hydrides at the interface between the silicon layer in interfacial and the dielectric layer.

18. The multilayer structure of claim 15 wherein the passivation layer has a thickness between about 0.1 nanometer and about 4 nanometers, as measured along the central axis.

Assignees

• Globalwafers Co Ltd

Inventors

• Wang Gang
• Thomas Shawn George

Classifications

• H10P14/2921

  being crystalline insulating materials · CPC title

• H10P90/1914

  using bonding · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P14/3822

  Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title