Methods of forming strained-semiconductor-on-insulator device structures

Patent metadata

Field	Value
Publication number	US-10510581-B2
Application number	US-201715400701-A
Country	US
Kind code	B2
Filing date	Jan 6, 2017
Priority date	Jun 7, 2002
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

First claim

What is claimed is:

1. A method comprising:
forming a graded buffer layer over a first substrate;
forming a relaxed layer over the graded buffer layer;
epitaxially growing a compressively strained semiconductor layer over the relaxed layer, the relaxed layer inducing strain in the compressively strained semiconductor layer, the compressively strained semiconductor layer having an initial misfit dislocation density;
bonding the compressively strained semiconductor layer directly to a second substrate, the compressive strain in the compressively strained semiconductor layer being substantially maintained after the bonding;
removing the first substrate, the graded buffer layer, and the relaxed layer from the compressively strained semiconductor layer, the compressively strained semiconductor layer remaining bonded to second substrate after the removing, wherein removing the first substrate reduces the initial misfit dislocation density in the compressively strained semiconductor layer; and
planarizing the compressively strained semiconductor layer where the relaxed layer has been removed, the planarizing the compressively strained semiconductor layer comprises an anneal performed at a temperature greater than approximately 800° C.

2. The method of claim 1 , wherein removing the first substrate comprises cleaving at a cleave plane in the relaxed layer.

3. The method of claim 1 , wherein the compressively strained semiconductor layer comprises at least one of a group II, a group III, a group IV, a group V, and a group VI element.

4. The method of claim 1 , wherein the compressively strained semiconductor layer comprises Si, Ge, SiGe, GaAs, indium phosphide (InP), zinc selenide (ZnSe), or a combination thereof.

5. The method of claim 1 further comprising:
before bonding, planarizing the compressively strained semiconductor layer.

6. The method of claim 1 , wherein the second substrate comprises Si, Ge, or SiGe.

7. The method of claim 1 , wherein removing the first substrate comprises cleaving, the cleaving separates the relaxed layer into two portions at a cleave plane.

8. The method of claim 1 , wherein the compressively strained semiconductor layer is the only compressively strained semiconductor layer on the first substrate, the compressively strained semiconductor layer being in direct contact with the relaxed layer.

9. The method of claim 1 , wherein removing the relaxed layer comprises:
oxidizing the relaxed layer; and
etching the oxidized relaxed layer.

10. A method comprising:
providing a first substrate having relaxed layer formed thereon and a compressively strained semiconductor layer formed on the relaxed layer, the relaxed layer inducing strain in the compressively strained semiconductor layer, the compressively strained semiconductor layer having an initial misfit dislocation density;
bonding the compressively strained semiconductor layer to an insulator layer disposed on a second substrate, the compressively strained semiconductor layer disposed between the relaxed layer and the insulator layer after the bonding;
removing the first substrate and the relaxed layer from the compressively strained semiconductor layer, the compressively strained semiconductor layer remaining bonded to the insulator layer;
planarizing the compressively strained semiconductor layer where the relaxed layer and the first substrate have been removed, the planarizing comprising an anneal performed at a temperature greater than approximately 800° C.; and
etching the planarized compressively strained semiconductor layer, wherein etching the planarized compressively strained semiconductor layer reduces the initial misfit dislocation density in the compressively strained semiconductor layer.

11. The method of claim 10 further comprising:
before bonding the compressively strained semiconductor layer to the insulator layer disposed on the second substrate, performing a plasma activation of at least one of a surface of the compressively strained semiconductor layer and a surface of the insulator layer.

12. The method of claim 10 further comprising:
before bonding the compressively strained semiconductor layer to the insulator layer disposed on the second substrate, planarizing by chemical-mechanical polishing a surface of the compressively strained semiconductor layer.

13. The method of claim 10 , wherein the bonding the compressively strained semiconductor layer comprises bonding the compressively strained semiconductor layer directly to the insulator layer disposed on the second substrate.

14. A method comprising:
providing a first substrate, a relaxed layer over the first substrate, and a compressively strained semiconductor layer over the relaxed layer, the relaxed layer inducing strain in the compressively strained semiconductor layer, the compressively strained semiconductor layer having an initial misfit dislocation density;
bonding the compressively strained semiconductor layer directly to an insulator layer disposed on a second substrate; and
removing the first substrate from the compressively strained semiconductor layer, the compressively strained semiconductor layer remaining bonded to the insulator layer, wherein removing the first substrate reduces the initial misfit dislocation density in the compressively strained semiconductor layer.

15. The method of claim 14 further comprising:
planarizing the compressively strained layer where the first substrate has been removed, the planarization comprising an anneal performed at a temperature greater than approximately 800° C.

16. The method of claim 14 , wherein removing the first substrate comprises cleaving at a cleave plane in the relaxed layer.

17. The method of claim 14 further comprising:
before bonding, planarizing the compressively strained semiconductor layer.

18. The method of claim 14 , wherein the second substrate comprises Si, Ge, or SiGe.

19. The method of claim 14 further comprising:
before bonding the compressively strained semiconductor layer to the insulator layer disposed on the second substrate, performing a plasma activation of at least one of a surface of the compressively strained semiconductor layer and a surface of the insulator layer.

20. The method of claim 14 , wherein providing the first substrate further comprises forming a graded buffer layer over the first substrate, the relaxed layer being over the graded buffer layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Langdo Thomas A
• Currie Matthew T
• Hammond Richard
• Lochtefeld Anthony J
• Fitzgerald Eugene A

Classifications

• H10P14/3402

  characterised by the chemical composition · CPC title

• H10P14/3251

  consisting of three or more layers · CPC title

• H10P14/3248

  consisting of two layers · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• H10P90/1924

  with separation/delamination along a porous layer · CPC title