Semiconductor memory device and method of testing the same

Patent metadata

Field	Value
Publication number	US-9455049-B2
Application number	US-201514702380-A
Country	US
Kind code	B2
Filing date	May 1, 2015
Priority date	Dec 19, 2014
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

A semiconductor memory device may include: a memory cell array including first and second word lines coupled to first and second memory cells, respectively; a word line driving unit suitable for selectively driving the first and second word lines; and a test control unit suitable for enabling the first word line to write test data to the first memory cell, and enabling the second word line to write the test data to the second memory cell, during a test operation.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a memory cell array comprising first and second word lines coupled to first and second memory cells, respectively;
a word line driving unit suitable for selectively driving the first and second word lines; and
a test control unit suitable for enabling the first word line to write test data to the first memory cell of a first bank, testing the second word line based on the test data written in the first word line, and enabling the second word line to write normal data to the second memory cell of a second bank, during a test operation,
wherein the first word line comprises a dummy word line, and the second word line comprises a plurality of normal word lines.

2. The semiconductor memory device of claim 1 , wherein the word line driving unit comprises:
a dummy word line driving unit suitable for driving the dummy word line in response to a first test signal; and
a normal word line driving unit suitable for driving the plurality of normal word lines in response to a second test signal.

3. The semiconductor memory device of claim 2 , wherein the test control unit generates the first test signal for controlling the dummy word line driving unit, and generates the second test signal which is activated after the dummy word line is enabled to write the test data to the first memory cell.

4. The semiconductor memory device of claim 1 , further comprising:
a plurality of bit lines crossing the first and second word lines; and
a bit line sense amplifier suitable for sensing and amplifying the test data loaded in the bit lines in response to a column select signal during a read operation.

5. The semiconductor memory device of claim 4 , further comprising:
a data input/output unit suitable for receiving the test data during a write operation and outputting the test data during the read operation.

6. The semiconductor memory device of claim 5 , wherein the data input/output unit comprises:
a write driver suitable for receiving input data as the test data to transfer the test data to the first memory cell, during the write operation; and
an input/output sense amplifier suitable for outputting the test data written in the second memory cell as output data, during the read operation.

7. The semiconductor memory device of claim 6 , further comprising:
a test determination unit suitable for comparing the output data with the input data and determining whether the second memory cell is normal or defective.

8. The semiconductor memory device of claim 7 , wherein the test determination unit comprises:
a comparison unit suitable for comparing the output data with the input data to output a comparison signal; and
a determination unit suitable for determining whether the second memory cell is normal or defective, in response to the comparison signal.

9. A method of testing a semiconductor memory device, the method comprising:
enabling a dummy word line in response to a first test signal;
writing test data to a first memory cell of a first bank coupled to the dummy word line;
enabling a normal word line of the first bank in response to a second test signal; and
writing the test data written in the first memory cell of the first bank to a second memory cell of a second bank coupled to the normal word line,
wherein the first bank and the second bank are different banks.

10. The method of claim 9 , further comprising:
reading the test data written in the second memory cell during a read operation; and
determining whether the second memory cell coupled to the normal word line is normal or defective, by comparing the test data written in the first memory cell with the test data read from the second memory cell.

11. The method of claim 10 , wherein the determining of whether the second memory cell coupled to the normal word line is normal or defective comprises:
comparing the test data written in the first memory cell with the test data read from the second memory cell, and outputting a comparison signal; and
determining whether the second memory cell coupled to the normal word line is normal or defective, in response to the comparison signal.

12. The method of claim 9 , wherein the second test signal is activated after enabling the dummy word line and writing the test data to the first memory cell coupled to the dummy word line.

13. The method of claim 9 , wherein the normal word line comprises a plurality of normal word lines.

14. A method of testing a semiconductor memory device, the method comprising:
enabling a dummy word line of a first bank during a test operation on the first bank;
writing test data to the dummy word line of the first bank;
testing a plurality of normal word lines of the first bank based on the test data written in the dummy word line of the first bank; and
writing normal data to a normal word line of a second bank while the plurality of normal word lines of the first bank are tested.

15. The method of claim 14 , wherein the testing of the plurality of normal word lines of the first bank comprises:
sequentially writing data to the plurality of normal word lines;
sequentially reading the data written in the plurality of normal word lines; and
comparing the written data with the read data.

16. The method of claim 14 , wherein the first and second banks perform a write operation through one write driver.

Assignees

• Sk Hynix Inc

Inventors

• Lee Sung-Yub
• Cho Na-Yeon

Classifications

• G11C29/025 Primary

  in signal lines · CPC title

• G11C29/08 Primary

  Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C7/06

  Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title